VHDL Shift Register - vhdl

Question

I am refreshing my VHDL programming skills (by using ModelSim), I wrote a Shift register project.
There is a problem, that I can't understand what should I do.
The problem is Q_out<=ACC; :when I wrote Q_out<=ACC inside the process, the data passed to Q_out at when the clk is going down, When i wrote Q_out<=ACC; after the process ended - Q_out changed when the clk is going up (as it meant to be) but at my test bench I see X instead of '1'...
what did I do wrong?
VHDL CODE:
Library ieee;
Use ieee.std_logic_1164.all;
Use work.New_Data_Pack.all;
Entity Shift_Reg IS
port(
Rst,Clk :IN std_logic;
Data :IN byte; -- std_logic_vector(7 downto 0);
Sel :IN t_shift; --sample, shl, shr, rotl, rotr
Q_out :OUT byte
);
End Shift_Reg;
ARCHITECTURE Shift_Reg_arc OF Shift_Reg IS
Signal ACC: byte:=(OTHERS=>'0'); -- std_logic_vector(7 downto 0);
BEGIN
ShiftPro:PROCESS (Rst,Clk)
BEGIN
IF Rst='1' Then
Q_out<=(OTHERS=>'0');
ACC<=(OTHERS=>'0');
ELSIF Clk'EVENT and Clk='1' THEN
CASE Sel is
WHEN sample=>
ACC<=Data;
WHEN shl=>
ACC<= ACC (6 downto 0) & '0'; -- & concatenation
WHEN shr=>
ACC<='0' & ACC (7 downto 1);
WHEN rotl=>
ACC<=ACC (6 downto 0)& ACC(7);
WHEN rotr=>
ACC<=ACC(0) & ACC(7 downto 1);
WHEN OTHERS=>
NULL;
END CASE;
END IF;
--Q_out<=ACC;
End PROCESS;
Q_out<=ACC;
End Shift_Reg_arc;
Test Bench:
Library ieee;
use ieee.std_logic_1164.all;
Use work.New_Data_Pack.all;
ENTITY Shift_Reg_TB IS END;
ARCHITECTURE Shift_Reg_TB_arc OF Shift_Reg_TB IS
---DUT Componenet Declaration
COMPONENT Shift_Reg
port(
Rst,Clk :IN std_logic;
Data :IN byte; -- std_logic_vector(7 downto 0);
Sel :IN t_shift; --sample, shl, shr, rotl, rotr
Q_out :OUT byte);
END COMPONENT;
-----Signal Declaration----
SIGNAL S_Clk,S_Rst :std_logic:='0';
SIGNAL S_Data, S_Q_out : byte;
SIGNAL S_Sel : t_shift;
SIGNAL S_Run :std_logic:='1';
BEGIN
-----DUT installation----
DUT: Shift_Reg
Port Map(S_Rst, S_Clk, S_Data, S_Sel, S_Q_out);
-----Signal Wave Creation----
S_Rst<='1' after 0ns, '0' after 80 ns;
S_Run<= '1' after 0ns, '0' after 600 ns;
S_Sel<= sample, shl after 150 ns, shr after 250 ns,sample after 350 ns, rotl after 450 ns, rotr after 550 ns;
S_Data<=X"45" after 0ns;--, "10" after 125 ns, "33" after 620 ns, x"44" after 720 ns;
---CLK Creation---------
S_Clk_Create:Process
BEGIN
while S_Run='1' loop
S_clk<='1', '0' after 50 ns;
Wait for 100 ns;
END LOOP;
S_clk<='1';
Wait;
END PROCESS;
END Shift_Reg_TB_arc;

Answer 1

You have conflicting drivers for Q_out. Either it must be driven sequentially by the process, or it is driven concurrently and can never be driven by the process. But right now you have both a concurrent assignment outside the process:
Q_out<=ACC;
and a sequential assignment inside the process
IF Rst='1' Then
Q_out<=(OTHERS=>'0');
You must delete the in-process reset when you move the clocked update outside the process.