this is vhdl code for an elevator for 7 floors
the coding is encapsulated into 3 states s0=no move ,s1=move up , s2 =move down
if it is in s0 it should wait for 2 cycles after that move up/down according to the desired floor or called floor on the next positive edge .
The problem is that the elevator is stuck in s1 state
could anyone help me please ?
-- Cad Project
-- Project Name : Elevator
-- Date : 18\12\2013
library IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--Entity Decleration
entity Elevator is
port (call, clk, press : in std_logic;
-- Call To Call The Elevator ,press if a key is pressrd from the pannel inside the elevator .
Desire_floor, Call_Floor : in std_logic_vector (2 downto 0);
-- Desired_floor is the floor number choosed from inside the elevator .
-- called_floor is the floor number that the "Call" Key has been pressed from .
weight : in std_logic;
Door_open_close, Move_up, move_down, OverWeight : out std_logic;
-- Door_open_close is 1 when opened ,0 when closed .
-- OverWeight is 1 when the weight is over 500 KG.
Current_Floor : buffer std_logic_vector (2 downto 0) := "000";
temp1_state, temp2_state : buffer std_logic_vector (1 downto 0);
o1, o2, o3, o4, o5, o6, o7 : out std_logic_vector (2 downto 0));
end;
--architecture Decleration
architecture Elevator of Elevator is
type state is (s0, s1, s2);
--s0 state represents no move ,s1 state represents move up ,s2 state represents move down .
signal current_state : state := s0;
signal next_state : state;
signal Desired_floor, Called_Floor : std_logic_vector (2 downto 0);
signal X : std_logic := '0'; -- X is a signal used to restart the timer or to resume it's count.
signal counter : std_logic_vector (2 downto 0); -- Timer befor closing/opening the doors "timer".
signal counter2 : std_logic_vector (2 downto 0) := "000"; -- Timer for the elevator to move up or down.
signal temp1, temp2, temp3, temp4, temp5 : std_logic_vector (2 downto 0);
begin
P1 : process (clk , weight, x)
variable s11 : std_logic_vector (2 downto 0) := "000";
-- Variable insted of the counter signal -->to have the direct assigment
begin
if (weight = '1') then
OverWeight <= '1';
current_state <= s0;
elsif (clk'event and clk = '1') then
if (x = '1') then -- if X equals to 1 that means restart the timer.
s11 := "000";
elsif (x = '0') then -- if X equals 0 then count up "keep counting ".
s11 := s11+1;
end if;
current_state <= next_state;
counter <= s11;
OverWeight <= '0';
end if;
counter <= s11;
o5 <= counter;
end process P1;
P2 : process (clk) -- this process if for the 2nd timer.
variable s4 : std_logic_vector (2 downto 0) := "000";
-- Variable insted of the counter2 signal -->to have the direct assigment
begin
if (rising_edge(clk)) then
if (press = '1') then
Desired_floor <= Desire_floor;
if (Current_Floor < Desired_floor) then
s4 := s4 +1;
elsif (Current_Floor > Desired_floor) then
s4 := s4 -1;
end if;
counter2 <= s4;
elsif (call = '1') then
Called_Floor <= Call_Floor;
if (Current_Floor < Called_Floor) then
s4 := s4 +1;
elsif (Current_Floor > Called_Floor) then
s4 := s4 -1;
end if;
end if;
end if;
counter2 <= s4;
o1 <= counter2;
o2 <= Desired_floor;
o3 <= Called_Floor;
counter2 <= s4;
--Desired_floor<=Desire_floor;
end process P2;
P3 : process (counter, current_state)
begin
case current_state is
when s0 =>
if(counter < "001") then
x <= '0';
Current_Floor <= Current_Floor;
next_state <= s0;
temp1_state <= "00";
else
if (press = '1') then
if(Desired_floor > Current_Floor) then
next_state <= s1;
temp2_state <= "01";
elsif (Desired_floor < Current_Floor) then
next_state <= s2;
temp2_state <= "10";
end if;
else
if (call = '1') then
if (Called_Floor > Current_Floor) then
next_state <= s1;
temp2_state <= "01";
elsif (Called_Floor < Current_Floor) then
next_state <= s2;
temp2_state <= "10";
end if;
end if;
end if;
x <= '1';
end if;
Door_open_close <= '1';
Move_up <= '0';
move_down <= '0';
Current_Floor <= counter2;
temp1_state <= "00";
when s1 =>
temp1 <= (Desired_floor - Current_Floor);
temp2 <= (Called_Floor-Current_Floor);
o4 <= temp1;
if ((temp1 /= "000") or (temp2 /= "000")) then
next_state <= s1;
temp2_state <= "01";
Current_Floor <= counter2;
elsif (((Desired_floor-Current_Floor) = "000")or ((Called_Floor-Current_Floor) = "000")) then
next_state <= s0;
temp2_state <= "00";
end if;
Door_open_close <= '0';
Move_up <= '1';
move_down <= '0';
Current_Floor <= counter2;
x <= '1';
temp1_state <= "01";
when s2 =>
temp3 <= (Current_Floor-Desired_floor);
temp4 <= (Current_Floor-Called_Floor);
if ((temp3 /= "000") or (temp4 /= "000")) then
next_state <= s2;
temp2_state <= "10";
Current_Floor <= counter2;
elsif (((Current_Floor-Desired_floor) = "000") or ((Called_Floor-Current_Floor) = "000")) then
next_state <= s0;
temp2_state <= "00";
end if;
Door_open_close <= '0';
Move_up <= '0';
move_down <= '1';
Current_Floor <= counter2;
x <= '1';
temp1_state <= "10";
end case;
end process P3;
end;
**********************************
I mad a lot of changes on the code and still have a problem .How can i save the value of an input at a certain state and ignore it's value until the next entering of the same state
-- Cad Project .
-- Project Name : Elevator .
-- Date : 18\12\2013.
-- Group Number : 13.
library IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--Entity Decleration
entity Elevator is
port (clk, press : in std_logic;
-- Call To Call The Elevator ,press if a key is pressrd from the pannel inside the elevator .
Desire_floor : in std_logic_vector (2 downto 0);
-- Desired_floor is the floor number choosed from inside the elevator .
-- called_floor is the floor number that the "Call" Key has been pressed from .
weight : in std_logic;
Door_open_close, Move_up, move_down, OverWeight : out std_logic;
-- Door_open_close is 1 when opened ,0 when closed .
-- OverWeight is 1 when the weight is over 500 KG.
Current_Floor : buffer std_logic_vector (2 downto 0) := "000";
temp1_state, temp2_state : buffer std_logic_vector (1 downto 0);
o1, o2, o3, o4, o5, o6, o7 : out std_logic_vector (2 downto 0));
end;
--architecture Decleration
architecture Elevator of Elevator is
type state is (s0, s1, s2);
--s0 state represents no move ,s1 state represents move up ,s2 state represents move down .
signal current_state : state := s0;
signal next_state : state;
signal Desired_floor : std_logic_vector (2 downto 0);
signal X : std_logic := '0'; -- X is a signal used to restart the timer or to resume it's count.
signal counter : std_logic_vector (2 downto 0); -- Timer befor closing/opening the doors "timer".
signal counter2 : std_logic_vector (2 downto 0) := "000"; -- Timer for the elevator to move up or down.
signal temp1, temp2, temp3, temp4, temp5 : std_logic_vector (2 downto 0);
signal temp6 : std_logic;
begin
P1 : process (clk , weight, x)
variable s11 : std_logic_vector (2 downto 0) := "000";
-- Variable insted of the counter signal -->to have the direct assigment
begin
if (weight = '1') then
OverWeight <= '1';
current_state <= s0;
elsif (clk'event and clk = '1') then
if (x = '1') then -- if X equals to 1 that means restart the timer.
s11 := "000";
elsif (x = '0') then -- if X equals 0 then count up "keep counting ".
s11 := s11+1;
end if;
current_state <= next_state;
counter <= s11;
OverWeight <= '0';
end if;
counter <= s11;
o5 <= counter;
end process P1;
P2 : process (clk) -- this process if for the 2nd timer.
variable s4 : std_logic_vector (2 downto 0) := "000";
-- Variable insted of the counter2 signal -->to have the direct assigment
begin
if (rising_edge(clk)) then
if (press = '1') then
if (Current_Floor < Desired_floor) then
s4 := s4 +1;
elsif (Current_Floor > Desired_floor) then
s4 := s4 -1;
end if;
counter2 <= s4;
end if;
end if;
counter2 <= s4;
o1 <= counter2;
o2 <= Desired_floor;
counter2 <= s4;
end process P2;
P3 : process (counter, current_state)
begin
case current_state is
when s0 =>
if(counter < "010") then
x <= '0';
Current_Floor <= Current_Floor;
next_state <= s0;
temp1_state <= "00";
else
if (press = '1') then
if(Desired_floor > Current_Floor) then
next_state <= s1;
temp2_state <= "01";
elsif (Desired_floor < Current_Floor) then
next_state <= s2;
temp2_state <= "10";
end if;
end if;
x <= '1';
end if;
Door_open_close <= '1';
Move_up <= '0';
move_down <= '0';
Current_Floor <= counter2;
temp1_state <= "00";
temp6 <= '1';
when s1 =>
temp1 <= (Desired_floor - Current_Floor);
o4 <= temp1;
if ((temp1 /= "000")) then
next_state <= s1;
temp2_state <= "01";
Current_Floor <= counter2;
elsif ((Desired_floor-Current_Floor) = "000") then
next_state <= s0;
temp2_state <= "00";
end if;
Door_open_close <= '0';
Move_up <= '1';
move_down <= '0';
Current_Floor <= counter2;
x <= '1';
temp1_state <= "01";
temp6 <= '0';
when s2 =>
temp3 <= (Current_Floor-Desired_floor);
if ((temp3 /= "000")) then
next_state <= s2;
temp2_state <= "10";
Current_Floor <= counter2;
elsif ((Current_Floor-Desired_floor) = "000") then
next_state <= s0;
temp2_state <= "00";
end if;
Door_open_close <= '0';
Move_up <= '0';
move_down <= '1';
Current_Floor <= counter2;
x <= '1';
temp1_state <= "10";
temp6 <= '0';
end case;
end process P3;
P4 : process (temp6, clk)
begin
if (clk 'event and clk = '1') then
if (temp6'event and temp6 = '1')then
--if ( current_state =s0 ) then
Desired_floor <= Desire_floor;
else
Desired_floor <= Desired_floor;
end if;
Desired_floor <= Desired_floor;
end if;
end process P4;
end;
It looks like the floor counter is only being incremented when the user presses 'press'.
Explanation
If we're not on the desired floor yet, then Current_Floor is driven by counter2
temp1 <= (Desired_floor - Current_Floor);
o4 <= temp1;
if ((temp1 /= "000")) then
next_state <= s1;
temp2_state <= "01";
Current_Floor <= counter2;
counter2 is driven by s4:
if (rising_edge(clk)) then
if (press = '1') then
if (Current_Floor < Desired_floor) then
s4 := s4 +1;
elsif (Current_Floor > Desired_floor) then
s4 := s4 -1;
end if;
counter2 <= s4; <-
end if;
end if;
counter2 <= s4; <-
o1 <= counter2;
o2 <= Desired_floor;
counter2 <= s4; <-
(Aside, why do you assign s4 to counter2 three times?)
s4 is only changed when press is asserted. So your lift is only going to be moving up or down a floor when someone pushes the button.
General comments
Your process sensitivity lists are all over the place! Your sensitivity lists should either be clock or clock,reset. Asynchronous processes (those without a clock in the sensitivity list) do have their place, but I generally avoid them unless absolutely necessary. I find it a lot easier to visualise the timing behaviour in my head when everything is strictly synchronous.
P1 : process (clk , weight, x) <- BAD
P2 : process (clk) <- GOOD
P3 : process (counter, current_state) <- OKAY
P4 : process (temp6, clk) <- BAD
Indenting has a huge impact on how you read the code. Learn to indent properly. I use the emacs VHDL mode, it has a great beautify function which really helps. I ran your code through it when I edited the comment and wrote this answer.
Your signal names need work. things like temp are a bad idea. you are doing pretty well with commenting though, so that's a plus. keep that up!
I'm going to briefly mention the code redundancy, example:
if (temp6'event and temp6 = '1')then
--if ( current_state =s0 ) then
Desired_floor <= Desire_floor;
else
Desired_floor <= Desired_floor;
end if;
Desired_floor <= Desired_floor;
If it was different before, totally understandable, but clean that stuff up, unnecessary reading for whoever is on the receiving end of your code.
Related
I'm working on an FSM for a quadrature encoder counter, to be used on the Arty A7 35 --- this is my first VHDL project, so I apologize if I am missing something very basic. I have an internal count signal that I decrement or increment in the FSM, but when I try to assign that signal via COUNT_OUT <= count, COUNT_OUT stays at zero, even though I have been able to observe the state changing. I do this assignment at the very end of the FSM process.
simulation outputs
Further, I am not able to observe "state", "next state", or "count" in simulation --- I would appreciate help on this as well as would be very useful. These signals do not show up in the "objects" window beside the scope either
My entity declaration is as follows:
entity GPIO_demo is
Port ( BTN : in STD_LOGIC;
z : in STD_LOGIC;
A : in STD_LOGIC;
B : in STD_LOGIC;
LED : out STD_LOGIC;
CLK : in STD_LOGIC;
UART_TXD : out STD_LOGIC;
COUNT_OUT : out unsigned(11 downto 0)
);
end GPIO_demo;
I define these relevant signals in architecture:
type state_type is (S00, S01, S10, S11);
signal state, next_state: state_type;
signal count: unsigned(11 downto 0) := (others=>'0');
My FSM is as follows:
SYNC_PROC: process(CLK)
begin
if rising_edge(CLK) then
if ( z='1' ) then
state <= S00;
count <= "000000000000";
else
state <= next_state;
end if;
end if;
end process;
NEXT_STATE_DECODE: process(state, A, B)
begin
case state is
when S00 =>
if(A = '0' and B = '1') then
count <= "000000000000";
next_state <= S01;
elsif(A = '1' and B = '0') then
count <= "000000000000";
next_state <= S10;
end if;
when S01 =>
if(A = '1' and B = '1') then
count <= "100000000000";
next_state <= S11;
elsif(A = '0' and B = '0') then
count <= "100000000000";
next_state <= S00;
end if;
when S11 =>
if(A = '1' and B = '0') then
count <= count - 1;
next_state <= S10;
elsif(A = '0' and B = '1') then
count <= count + 1;
next_state <= S01;
end if;
when S10 =>
if(A = '0' and B = '0') then
count <= count - 1;
next_state <= S00;
elsif(A = '1' and B = '1') then
count <= count + 1;
next_state <= S11;
end if;
end case;
COUNT_OUT <= count;
end process;
Any idea on why this output does not update?
I am trying to write a program to detect if a given input is a prime number or not. When I run the test bench I get correct results however when I run it on the FPGA it only recognizes numbers that are divisible 3 or even as not prime. Any number such as 25 which is divisible by 5 will result in isPrime being 1. What could be causing this inconsistent result?
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE IEEE.std_logic_unsigned.all;
USE IEEE.numeric_std.all;
entity PrimeNumber is
Port ( clk: in std_logic;
rst : in std_logic;
input: in std_logic_vector(15 downto 0);
isPrime: out std_logic:= '0';
testOut: out std_logic_vector(31 downto 0)
);
end PrimeNumber;
architecture Behavioral of PrimeNumber is
SIGNAL current_state: std_logic_vector(2 downto 0);
signal next_state: std_logic_vector(2 downto 0):= "000";
signal max: integer;
signal temp: integer;
signal x: integer;
signal nextX:integer;
signal localPrime : std_logic:= '0';
signal current : integer;
signal update: std_logic := '0';
begin
nextX <= x +2;
process(current_state,input)
begin
case (current_state) is
when "000" => --Initial State
update <= '0';
localPrime <= '0';
if(input < x"0004")then
next_state <= "111";
else
max <= to_integer(unsigned(input(15 downto 1)));
current <=to_integer(unsigned(input));
if(input(0) = '0')then
next_state <= "110";
else
next_state <= "001";
end if;
end if;
when "001" => -- Computation State
localPrime <= '0';
temp <= current mod x;
if(x > max) then
next_state <= "111";
else
next_state <= "010";
end if;
update <= '1';
when "010" => -- Checking State
update <= '0';
localPrime <= '0';
if(temp = 0) then
next_state <= "110";
else
next_state <= "001";
end if;
when "110" =>
localPrime <= '0'; -- Not Prime State
next_state <= "110";
when "111" =>
update <= '0';
localPrime <= '1'; --Prime State
next_state <= "111";
when others =>
temp <= 0;
localPrime <= '0';
next_state <= "000";
end case;
end process;
Update_Registers: process(clk)
begin
if(clk'event and clk = '1') then
if ( rst = '1') then
current_state <= "000";
isPrime <= '0';
x<=3;
else
if(update = '1') then
x <= nextX;
end if;
current_state <= next_state;
isPrime <= localPrime;
end if;
end if;
end process;
end Behavioral;
To quickly check sim/syn mismatch, with the visibility you need outside of HW: output the mod result to a port, sim, should still "work"... syn, compile your (hopefully, verilog) netlist for TB, point to compiled netlist, sim, check the mod result against RTL/expected results.
I build a 4 bit sequence detector with a 16-bit input.
I wanna now how often the sequence appears in the 16 bits.
For that I use this code:
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
ENTITY seqdec IS
PORT ( X: IN std_logic_vector(15 DOWNTO 0);
CLK: IN std_logic;
RESET:IN std_logic;
LOAD: IN std_logic;
Y: OUT std_logic);
END seqdec;
ARCHITECTURE SEQ OF seqdec IS
TYPE statetype IS (s0, s1, s2, s3, s4);
SIGNAL state, next_state: statetype;
SIGNAL counter: std_logic_vector(3 DOWNTO 0) :="0000" ;
SIGNAL temp: std_logic_vector(15 DOWNTO 0);
SIGNAL so: std_logic;
BEGIN
STATE_AKT: PROCESS (CLK, RESET)
BEGIN
IF RESET = '1' THEN
state <= s0 ;
counter <= (OTHERS => '0') ;
ELSIF CLK = '1' AND CLK'event THEN
state <= next_state ;
END IF;
END PROCESS STATE_AKT;
PISO: PROCESS (CLK, LOAD, X)
BEGIN
IF (LOAD = '1') THEN
temp(15 DOWNTO 0) <= X(15 DOWNTO 0);
ELSIF (CLK'event and CLK='1') THEN
so <= temp(15) ;
temp(15 DOWNTO 1) <= temp(14 DOWNTO 0);
temp(0) <= '0';
END IF;
END PROCESS PISO;
STATE_CAL: PROCESS (so,state)
BEGIN
CASE state IS
WHEN s0 => IF so = '0' THEN next_state <= s0 ;
ELSE next_state <= s1 ;
END IF;
WHEN s1 => IF so = '0' THEN next_state <= s1;
ELSE next_state <= s2 ;
END IF;
WHEN s2 => IF so = '0' THEN next_state <= s3 ;
ELSE next_state <= s2 ;
END IF;
WHEN s3 => IF so = '0' THEN next_state <= s0 ;
ELSE next_state <= s4 ;
END IF;
WHEN s4 => IF so = '0' THEN next_state <= s0;
ELSE next_state <= s2 ;
END IF;
WHEN OTHERS => NULL;
END CASE;
END PROCESS STATE_CAL;
STATE_Y: PROCESS (state)
BEGIN
CASE state IS
WHEN s4 =>
Y <= '1';
counter <= counter + '1';
WHEN OTHERS => Y <= '0' ;
END CASE;
END PROCESS STATE_Y;
END SEQ;
But neither my counter reset nor my incrementation of counter is working.
The rest is working perfect and fine.
Has somebody a hint or an idea for me?
The programm is now working fine in ModelSim, but I struggle with getting it on the board.
I simulated it several times in ModelSim, with different parameters and it works fine, so the functional part is fine.
My code looks now this way:
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
ENTITY seqdec IS
PORT ( X: IN std_logic_vector(15 DOWNTO 0);
CLK: IN std_logic;
RESET: IN std_logic;
LOAD: IN std_logic;
DIGIT: OUT std_logic_vector(6 DOWNTO 0) := "1111110";
COUT: OUT std_logic_vector(2 DOWNTO 0);
Y: OUT std_logic);
END seqdec;
ARCHITECTURE SEQ OF seqdec IS
TYPE statetype IS (s0, s1, s2, s3, s4);
SIGNAL state: statetype;
SIGNAL next_state: statetype:=s0;
SIGNAL counter: std_logic_vector(2 DOWNTO 0) :="000" ;
SIGNAL temp: std_logic_vector(15 DOWNTO 0);
SIGNAL so: std_logic := 'U';
-------------------Aktualisierung des Zustandes--------------------------------
BEGIN
STATE_AKT: PROCESS (CLK, RESET)
BEGIN
IF RESET = '1' THEN
state <= s0;
ELSIF CLK = '1' AND CLK'event THEN
state <= next_state ;
END IF;
END PROCESS STATE_AKT;
---------------------Counter---------------------------------------------------
COUNT: PROCESS (state, RESET)
BEGIN
IF (RESET = '1') THEN
counter <= (OTHERS => '0');
ELSIF (state = s4) THEN
counter <= counter + '1';
COUT <= counter;
END IF;
END PROCESS COUNT;
-------------------PiSo für die Eingabe des zu Prüfenden Vektors---------------
PISO: PROCESS (CLK, LOAD, X)
BEGIN
IF (LOAD = '1') THEN
temp(15 DOWNTO 0) <= X(15 DOWNTO 0);
ELSIF (CLK'event and CLK='1') THEN
so <= temp(15);
temp(15 DOWNTO 1) <= temp(14 DOWNTO 0);
temp(0) <= '0';
END IF;
END PROCESS PISO;
-------------------Zustandsabfrage und Berechnung------------------------------
STATE_CAL: PROCESS (so,state)
BEGIN
CASE state IS
WHEN s0 => IF so = '0' THEN next_state <= s0 ;
ELSIF (so = '1') THEN next_state <= s1 ;
END IF;
WHEN s1 => IF so = '0' THEN next_state <= s1;
ELSIF (so = '1') THEN next_state <= s2 ;
END IF;
WHEN s2 => IF so = '0' THEN next_state <= s3 ;
ELSIF (so = '1') THEN next_state <= s2 ;
END IF;
WHEN s3 => IF so = '0' THEN next_state <= s0 ;
ELSIF (so = '1') THEN next_state <= s4 ;
END IF;
WHEN s4 => IF so = '0' THEN next_state <= s0;
ELSIF (so = '1') THEN next_state <= s2 ;
END IF;
WHEN OTHERS => NULL;
END CASE;
END PROCESS STATE_CAL;
-------------------Ausgang-----------------------------------------------------
STATE_Y: PROCESS (state)
BEGIN
CASE state IS
WHEN s4 =>
Y <= '1';
WHEN OTHERS => Y <= '0' ;
END CASE;
END PROCESS STATE_Y;
-------------------7 Segment---------------------------------------------------
SEVEN_SEG: PROCESS (counter, CLK)
BEGIN
IF (RESET = '1') THEN
DIGIT <= "1111110";
END IF;
CASE counter IS
WHEN "000" => DIGIT <= "1111110";
WHEN "001" => DIGIT <= "0110000";
WHEN "010" => DIGIT <= "1101101";
WHEN "011" => DIGIT <= "1111001";
WHEN "100" => DIGIT <= "0110011";
WHEN "101" => DIGIT <= "1011011";
WHEN OTHERS => NULL;
END CASE;
END PROCESS SEVEN_SEG;
END SEQ;
When i put it on the board the 7-segment will show a "3".
I would assume, as the functional part seems to be good,that it has to do somethink with the timings, but i can't find any solution to it. If some experience VHDL-programmer could give me a new hint that would be great.
Best regards
Adrian
I have updated the program, it does finish but now I am trying simulate the project. I am able to get the clock clear and lights on the pins, but I am not able to get the lights to work and count and states are not even showing. I believe I have this all set correctly but I could be wrong. Thank you once again Morten Zilmer for the help with the Error code.
http://tinypic.com/r/24yog0z/8
This is the simulation of the file,
entity traffic is
port (clk: in std_logic;
clr: in std_logic;
lights: out std_logic_vector (5 downto 0));
end traffic;
architecture traffic of traffic is
type state_type is (s0, s1, s2, s3, s4, s5);
signal state: state_type;
signal count : std_logic_vector (3 downto 0);
constant sec5: std_logic_vector (3 downto 0) := "1111";
constant sec1: std_logic_vector (3 downto 0) := "0011";
begin
process(clk, clr)
begin
if clr = '1' then
state<= s0;
count <= x"0";
elsif (clk'event and clk = '1') then
case state is
when s0 =>
if count <= sec5 then
state <= s0;
count <= count +1;
else
state <= s1;
count <= x"0";
end if;
when s1 =>
if count <= sec1 then
state <= s1;
count <= count +1;
else
state <= s2;
count <= x"0";
end if;
when s2 =>
if count <= sec1 then
state <= s2;
count <= count +1;
else
state <= s3;
count <= x"0";
end if;
when s3 =>
if count <= sec5 then
state <= s3;
count <= count +1;
else
state <= s4;
count <= x"0";
end if;
when s4 =>
if count <= sec1 then
state <= s4;
count <= count +1;
else
state <= s5;
count <= x"0";
end if;
when s5 =>
if count <= sec1 then
state <= s5;
count <= count +1;
else
state <= s0;
count <= x"0";
end if;
when others =>
state <= s0;
end case;
end if;
end process;
c2 : process (state)
begin
case state is
when s0 => lights <= "100001";
when s1 => lights <= "100010";
when s2 => lights <= "100100";
when s3 => lights <= "001100";
when s4 => lights <= "010100";
when s5 => lights <= "100100";
when others => lights <= "100001";
end case;
end process;
end traffic;
Change elseif to elsif, for valid VHDL syntax.
I am attempting to write a Successive Approximation Register in VHDL for an ADC. I am making it a state machine. I am just a little unsure about my code in the final State block (current_state = S_LSB). Is this code valid? Is there a better way to reset DigitalOutTemp and OutTemp before going back to state one?
NOTE The value of Comparator depends on the DigitalOutTemp output after it goes through a Digital to Analog Converter.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY SARegister IS
PORT (
Comparator, Clock : IN std_logic;
DigitalOutFinal, DigitalOutTemp : OUT std_logic_vector (13 downto 0)
);
END;
ARCHITECTURE Behavioural OF SARegister IS
CONSTANT S_MSB : STD_LOGIC_VECTOR(3 downto 0) := "0000";
CONSTANT S_TWELVE : STD_LOGIC_VECTOR(3 downto 0) := "0001";
CONSTANT S_ELEVEN : STD_LOGIC_VECTOR(3 downto 0) := "0010";
CONSTANT S_TEN : STD_LOGIC_VECTOR(3 downto 0) := "0011";
CONSTANT S_NINE : STD_LOGIC_VECTOR(3 downto 0) := "0100";
CONSTANT S_EIGHT : STD_LOGIC_VECTOR(3 downto 0) := "0101";
CONSTANT S_SEVEN : STD_LOGIC_VECTOR(3 downto 0) := "0110";
CONSTANT S_SIX : STD_LOGIC_VECTOR(3 downto 0) := "0111";
CONSTANT S_FIVE : STD_LOGIC_VECTOR(3 downto 0) := "1000";
CONSTANT S_FOUR : STD_LOGIC_VECTOR(3 downto 0) := "1001";
CONSTANT S_THREE : STD_LOGIC_VECTOR(3 downto 0) := "1010";
CONSTANT S_TWO : STD_LOGIC_VECTOR(3 downto 0) := "1011";
CONSTANT S_ONE : STD_LOGIC_VECTOR(3 downto 0) := "1100";
CONSTANT S_LSB : STD_LOGIC_VECTOR(3 downto 0) := "1101";
SIGNAL Next_state : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL Current_state : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL OutTemp : STD_LOGIC_VECTOR(13 DOWNTO 0);
BEGIN
PROCESS (Clock)
BEGIN
IF (rising_edge (Clock)) THEN
Current_state <= Next_state;
END IF;
END PROCESS;
PROCESS (Current_state, Comparator)
BEGIN
Next_state <= Current_state;
DigitalOutTemp <= "10000000000000";
OutTemp <= "10000000000000";
DigitalOutFinal <= "00000000000000";
IF (Current_state = S_MSB) THEN
IF (Comparator = '0') THEN
DigitalOutTemp(13) <= '0';
OutTemp(13) <= '0';
END IF;
DigitalOutTemp(12) <='1';
OutTemp(12) <= '1';
Next_state <= S_TWELVE;
ELSIF (Current_state = S_TWELVE) THEN
IF (Comparator = '0') THEN
DigitalOutTemp(12) <= '0';
OutTemp(12) <= '0';
END IF;
DigitalOutTemp(11) <='1';
OutTemp(11) <= '1';
Next_state <= S_ELEVEN;
ELSIF (Current_state = S_ELEVEN) THEN
IF (Comparator = '0') THEN
DigitalOutTemp(11) <= '0';
OutTemp(11) <= '0';
END IF;
DigitalOutTemp(10) <='1';
OutTemp(10) <= '1';
Next_state <= S_TEN;
ELSIF (Current_state = S_TEN) THEN
IF (Comparator = '0') THEN
DigitalOutTemp(10) <= '0';
OutTemp(10) <= '0';
END IF;
DigitalOutTemp(9) <='1';
OutTemp(9) <= '1';
Next_state <= S_NINE;
ELSIF (Current_state = S_NINE) THEN
IF (Comparator = '0') THEN
DigitalOutTemp(9) <= '0';
OutTemp(9) <= '0';
END IF;
DigitalOutTemp(8) <='1';
OutTemp(8) <= '1';
Next_state <= S_EIGHT;
ELSIF (Current_state = S_EIGHT) THEN
IF (Comparator = '0') THEN
DigitalOutTemp(8) <= '0';
OutTemp(8) <= '0';
END IF;
DigitalOutTemp(7) <='1';
OutTemp(7) <= '1';
Next_state <= S_SEVEN;
ELSIF (Current_state = S_SEVEN) THEN
IF (Comparator = '0') THEN
DigitalOutTemp(7) <= '0';
OutTemp(7) <= '0';
END IF;
DigitalOutTemp(6) <='1';
OutTemp(6) <= '1';
Next_state <= S_SIX;
ELSIF (Current_state = S_SIX) THEN
IF (Comparator = '0') THEN
DigitalOutTemp(6) <= '0';
OutTemp(6) <= '0';
END IF;
DigitalOutTemp(5) <='1';
OutTemp(5) <= '1';
Next_state <= S_FIVE;
ELSIF (Current_state = S_FIVE) THEN
IF (Comparator = '0') THEN
DigitalOutTemp(5) <= '0';
OutTemp(5) <= '0';
END IF;
DigitalOutTemp(4) <='1';
OutTemp(4) <= '1';
Next_state <= S_FOUR;
ELSIF (Current_state = S_FOUR) THEN
IF (Comparator = '0') THEN
DigitalOutTemp(4) <= '0';
OutTemp(4) <= '0';
END IF;
DigitalOutTemp(3) <='1';
OutTemp(3) <= '1';
Next_state <= S_THREE;
ELSIF (Current_state = S_THREE) THEN
IF (Comparator = '0') THEN
DigitalOutTemp(3) <= '0';
OutTemp(3) <= '0';
END IF;
DigitalOutTemp(2) <='1';
OutTemp(2) <= '1';
Next_state <= S_TWO;
ELSIF (Current_state = S_TWO) THEN
IF (Comparator = '0') THEN
DigitalOutTemp(2) <= '0';
OutTemp(2) <= '0';
END IF;
DigitalOutTemp(1) <='1';
OutTemp(1) <= '1';
Next_state <= S_ONE;
ELSIF (Current_state = S_ONE) THEN
IF (Comparator = '0') THEN
DigitalOutTemp(1) <= '0';
OutTemp(1) <= '0';
END IF;
DigitalOutTemp(0) <='1';
OutTemp(0) <= '1';
Next_state <= S_LSB;
ELSIF (Current_state = S_LSB) THEN
IF (Comparator = '0') THEN
DigitalOutTemp(0) <= '0';
OutTemp(0) <= '0';
END IF;
DigitalOutFinal <= OutTemp;
DigitalOutTemp <= "10000000000000";
OutTemp <= "10000000000000";
Next_state <= S_MSB;
END IF;
END PROCESS;
END;
Its hard to tell what your code is trying to accomplish, so I thought I'd make some general observations that might help you along.
There is a lot of needless repetition in your code that you can fix by using a counter to index your bits rather than a hard coded index in each state, for example using a counter idx that counts from your MSB to LSB you can do:
...
elsif (current_state = COMPARE) then
OutTemp(idx) <= comparator;
if idx > 0 then
OutTemp(idx-1) <= '1';
idx <= idx - 1;
next_state <= current_state;
else
idx <= MSB;
next_state <= idle;
end if;
end if;
This assumes you want to set OutTemp(idx-1) in the previous state, which strikes me as a bit pointless, but maybe its required by your external hardware...
You have also duplicated your OutTemp by assigning to both a signal and a port, I would remove all your assignments to the port DigitalOutTemp and instead add the following to your clocked process:
process (clock)
begin
if rising_edge(clock) then
Current_state <= Next_state;
DigitalOutTemp <= OutTemp;
end if;
end process;
This will set DigitalOutTemp synchronously, if you dont want this you can set it outside of the clocked process instead, but I would advise you to set it synchronously to avoid glitches.
To answer your question, the final state:
ELSIF (Current_state = S_LSB) THEN
IF (Comparator = '0') THEN
DigitalOutTemp(0) <= '0';
OutTemp(0) <= '0';
END IF;
DigitalOutFinal <= OutTemp;
DigitalOutTemp <= "10000000000000";
OutTemp <= "10000000000000";
Next_state <= S_MSB;
END IF;
.. will just set DigitalOutTemp to "10000000000000" and DigitalOutFinal to whatever was in OutTemp in the previous state. It appears that you expect OutTemp to have been updated by the assignment to OutTemp(0) further up, but this wont be the case. The assignment to OutTemp(0) is scheduled for the end of the process; it isn't visible immediately.
The assignments to OutTemp(0) and DigitalOutTemp(0) in the IF statement will do nothing as their scheduled writes are cancelled by your assignments to them further down.
So to answer your question, it looks like valid code in that it will probably compile and synthesize, but it wont exhibit the behaviour you seem to expect.
Hope this helps.