I am getting this error in my VHDL code :
found '0' definitions of operator "=", cannot determine exact
overloaded matching definition for "="
Here is my code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
entity test2 is
Port (clk : in std_logic ;
sclk : out std_logic);
end test2;
architecture Behavioral of test2 is
signal cnt : std_logic_vector(2 downto 0):=(others=>'0');
begin
process(clk)
begin
if rising_edge(clk) then
if cnt(2) = "111" then
sclk <= clk ;
else
cnt <= cnt+1;
end if;
end if;
end process;
end Behavioral;
Where exactly is the problem?
the "cnt" is 3bit signal like (bit2,bi1,bit0). When you write cnt(2) it will mean cnt(bit2), however you compared it with "111".
Related
My code will not simulate an output when running the VWF file.
I have tried changing the code several different time and don't really understand what I'm doing wrong.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Counter_JM is
Port (
up_down : in std_logic;
LED : out std_logic;
Q : Buffer integer Range 0 to 7);
end Counter_JM;
architecture archi of Counter_JM is
Begin
-- up/down counter
process (up_down)
begin
if (Q=7) then
Q<=0;
end if;
if (up_down = '1') then
Q <= Q + 1;
else
Q<=0;
end if;
if (Q=0 or Q=1) then
LED <= '0';
else
LED <= '1';
end if;
end process;
end archi;
The LED output should show high for 4 cycles and low for 2 on the VWF file
I don't know why you use up_down. But as Oldfart said, you don't have a clock. I have simplified and modified your code (it works for me (in modelsim):
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Counter_JM is
Port (
clk: in std_logic;
up_down : in std_logic;
LED : out std_logic
);
end Counter_JM;
architecture archi of Counter_JM is
Begin
process (clk)
variable Q: integer range 0 to 7;
begin
if rising_edge(clk) then
-- up/down counter
Q := Q + 1;
if Q=1 or Q=2 then
LED <= '0';
else
LED <= '1';
end if;
if Q = 7 then
Q := 0;
end if;
end if;
end process;
end archi;
and also created/generated a simple testbench here :
`-- Testbench automatically generated online
-- at http://vhdl.lapinoo.net
-- Generation date : 7.6.2019 11:22:53 GMT
library ieee;
use ieee.std_logic_1164.all;
entity tb_Counter_JM is
end tb_Counter_JM;
architecture tb of tb_Counter_JM is
component Counter_JM
port (clk : in std_logic;
up_down : in std_logic;
LED : out std_logic);
end component;
signal clk : std_logic;
signal up_down : std_logic;
signal LED : std_logic;
constant TbPeriod : time := 1000 ns; -- EDIT Put right period here
signal TbClock : std_logic := '0';
signal TbSimEnded : std_logic := '0';
begin
dut : Counter_JM
port map (clk => clk,
up_down => up_down,
LED => LED);
-- Clock generation
TbClock <= not TbClock after TbPeriod/2 when TbSimEnded /= '1' else '0';
-- EDIT: Check that clk is really your main clock signal
clk <= TbClock;
stimuli : process
begin
-- EDIT Adapt initialization as needed
up_down <= '0';
-- EDIT Add stimuli here
wait for 100 * TbPeriod;
-- Stop the clock and hence terminate the simulation
TbSimEnded <= '1';
wait;
end process;
end tb;
-- Configuration block below is required by some simulators. Usually no need to edit.
configuration cfg_tb_Counter_JM of tb_Counter_JM is
for tb
end for;
end cfg_tb_Counter_JM;`
I want to have two combinational processes driving one signal in wired-or style. Each process can drive 'Z' or '1' value to the signal and there is a global pull-down to 'L'.
Vivado 2017.1 synthesis 'optimizes' my code to drive a constant 0 to the output port. Why does this happen? How do I work around this issue?
Code:
library ieee;
use ieee.std_logic_1164.all;
entity test is
port(
input_0 : in std_logic;
input_1 : in std_logic;
output : out std_logic
);
end entity test;
architecture rtl of test is
signal s_output : std_logic;
begin
output <= to_X01(to_bit(s_output));
process(input_0)
begin
s_output <= 'Z';
if input_0='1' then
s_output <= '1';
end if;
end process;
process(input_1)
begin
s_output <= 'Z';
if input_1='1' then
s_output <= '1';
end if;
end process;
s_output <= 'L';
end architecture rtl;
Synthesis result:
WARNING: [Synth 8-3917] design test has port output driven by constant 0
I have been stuck with this problem for a while. I would be really grateful if someone is able help. Have gone through most of the code repeatedly without any solution. There are sets of codes in use; this bcd counter is used further in the rest of my project. I have added the necessary codes below:
BCD counter for 1 digit:
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE WORK.mypackage_p.ALL;
ENTITY bcd_e IS
PORT(
res_i, clk_i, enable_i, counter_res_i : IN STD_LOGIC;
bcd_o : OUT STD_LOGIC_VECTOR(bcd_width_c-1 DOWNTO 0);
carry_o : OUT STD_LOGIC
);
END bcd_e;
ARCHITECTURE bcd_a OF bcd_e IS
SIGNAL count_s : INTEGER RANGE bcd_cnt_c DOWNTO 0;
BEGIN
PROCESS(res_i, clk_i)
BEGIN
IF (res_i = '1') THEN
count_s <= 0;
ELSIF (clk_i = '1' AND clk_i'EVENT) THEN
IF (enable_i = '1') THEN
IF(count_s >= bcd_cnt_c) THEN
count_s <= 0;
ELSE
count_s <= count_s + 1;
END IF;
END IF;
IF (counter_res_i = '1') THEN
count_s <= 0;
END IF;
END IF;
END PROCESS;
bcd_o <= STD_LOGIC_VECTOR(to_unsigned(count_s, bcd_width_c));
carry_o <= '1' WHEN (count_s = bcd_cnt_c) ELSE '0';
END bcd_a;
8 digit BCD using the above bcd counter to create 8 digits
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE WORK.mypackage_p.ALL;
ENTITY bcd_8counter_e IS
PORT(
res_i, clk_i, enable_i, counter_res_i : IN STD_LOGIC;
bcd_array_o : OUT bcd_array_t
);
END bcd_8counter_e;
ARCHITECTURE bcd_8counter_a OF bcd_8counter_e IS
COMPONENT bcd
PORT(
res_i, clk_i, enable_i, counter_res_i : IN STD_LOGIC;
bcd_o : OUT STD_LOGIC_VECTOR(bcd_width_c-1 DOWNTO 0);
carry_o : OUT STD_LOGIC
);
END COMPONENT;
SIGNAL bcd_array_s : bcd_array_t;
SIGNAL enable_s : STD_LOGIC_VECTOR(no_of_digits_c-1 DOWNTO 0);
SIGNAL carry_s : STD_LOGIC_VECTOR(no_of_digits_c-1 DOWNTO 0);
FOR ALL : bcd USE ENTITY WORK.bcd_e (bcd_a);
BEGIN
carry_s(0) <= enable_i;
gen_carry : FOR i IN 1 TO (no_of_digits_c-1) GENERATE
carry_s(i) <= carry_s((i-1)) AND enable_s((i-1));
END GENERATE gen_carry;
gen_bcd : FOR i IN 0 TO (no_of_digits_c-1) GENERATE
digitx : bcd PORT MAP(res_i, clk_i, carry_s(i), counter_res_i, bcd_array_s(i), enable_s(i));
END GENERATE gen_bcd;
bcd_array_o <= bcd_array_s
END bcd_8counter_a;
My package file for the constants:
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
PACKAGE mypackage_p IS
CONSTANT freq_20k_c : INTEGER := 2500;
CONSTANT bcd_cnt_c : INTEGER := 9;
CONSTANT bcd_width_c : INTEGER := 4;
CONSTANT no_of_digits_c : INTEGER := 8;
TYPE bcd_array_t IS ARRAY(7 DOWNTO 0) OF STD_LOGIC_VECTOR(3 DOWNTO 0);
END PACKAGE;
I keep getting the following warning:
Warning: /home/stud/mr-131416/Desktop/VHDL_Project_Latest/src/bcd_counter8_a.vhd(15): (vcom-1263) Configuration specification "all : bcd" applies to no component instantiation statements.
The code does not pass test/simulation of a test-bench because of this warning. Help would be really appreciated.
It's a matter of scope. A component configuration configures a component instantiation. The generate statement produces a block statement (or nested block statements when a port map is supplied).
A block statement (for an internal or external block) use a block configuration which is only found in a configuration declaration.
Binding indications are not hierarchical, without the ability to reach down into a block to specify a component instantiation you can either use a configuration declaration or move the configuration specification:
-- for all : bcd use entity work.bcd_e (bcd_a);
begin
carry_s(0) <= enable_i;
gen_carry :
for i in 1 to (no_of_digits_c-1) generate
carry_s(i) <= carry_s((i-1)) and enable_s((i-1));
end generate gen_carry;
gen_bcd :
for i in 0 to (no_of_digits_c-1) generate
for all: bcd use entity work.bcd_e (bcd_a);
begin
digitx : bcd port map (res_i, clk_i, carry_s(i),
counter_res_i, bcd_array_s(i), enable_s(i));
end generate gen_bcd;
bcd_array_o <= bcd_array_s; -- CHANGED WAS MISSING SEMICOLON
end bcd_8counter_a;
Note the missing semicolon on the assignment statement for bcd_array_o has been added.
With these changes your design analyzes and elaborates without warnings.
You could note not all synthesis tools support configuration declarations while most support configuration specifications.
See IEEE Std 1076-2008 7.3 Configuration specification, 3.4 Configuration declarations, 3.4.2 Block configurations
The failure to simulate or synthesize would be because the distx component instantiations are unbound because there isn't a bcd entity found in the working directory.
Writing a simple testbench that does not invoke the synchronous reset, uses a clock with a 10 ns period and runs for 10 ms:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mypackage_p.all;
entity tb is
end entity;
architecture foo of tb is
signal reset: std_logic; -- '1' for RESET
signal clk: std_logic := '0';
signal en: std_logic; -- '1' for ENABLE
signal syn_reset: std_logic; -- '1' for SYNCHRONOUS RESET
signal bcd_array: bcd_array_t;
begin
DUT:
entity work.bcd_8counter_e
port map (
res_i => reset,
clk_i => clk,
enable_i => en,
counter_res_i => syn_reset,
bcd_array_o => bcd_array
);
CLOCK:
process
begin
wait for 5 ns;
clk <= not clk;
if now > 10 ms then
wait;
end if;
end process;
STIMULI:
process
begin
wait for 10 ns;
reset <= '0';
en <= '0';
syn_reset <= '0';
wait for 10 ns;
reset <= '1';
wait for 20 ns;
reset <= '0';
wait for 20 ns;
en <= '1';
wait;
end process;
end architecture;
Shows that the counter depends on enable and shows that the first 6 digits work:
In my VHDL code I have an error in sig_out_real <= X"00" & sig_in when sig_in(7)='0' else X"ff" & sig_in;.
I don't think it is a syntax error. But Quartus shows an error at that point.
I don`t understand why it's an error.
Can anyone provide information:
-- Error--
Error (10500): VHDL syntax error at S8BT16B.vhd(35) near text "when"; expecting ";"
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
use ieee.std_logic_arith.all;
use work.fft_package.all;
entity S8BT16B is
port(
clk_50 : in std_logic;
clk_baud : in std_logic;
main_reset : in std_logic;
enable : in std_logic;
sig_in : in signed (7 downto 0);
sig_out : out complex;
valid_output : out std_logic
);
end S8BT16B;
architecture Behavioral of S8BT16B is
type state is (idle,start);
signal state_reg, next_state_reg : state;
signal sig_out_real : signed(15 downto 0);
begin
state_change : process(clk_50, main_reset)
begin
if (main_reset = '1' or enable = '0') then
state_reg <= idle;
elsif (main_reset ='0' and enable = '1') then
state_reg <= next_state_reg;
end if;
end process;
S8BT16B_active : process(clk_baud, state_reg)
begin
if (state_reg = idle) then
sig_out_real <="0000000000000000";
sig_out <=(sig_out_real,"0000000000000000");
next_state_reg <= start;
valid_output <= '0';
elsif (state_reg = start and enable = '1') then
sig_out_real <= X"00" & sig_in when sig_in(7)='0' else X"ff" & sig_in;
sig_out <= (signed_converted_input, "0000000000000000");
next_state_reg <= idle;
valid_output <= '1';
end if;
end process;
end Behavioral;
You code does not present a Minimal, Complete, and Verifiable example.
The package fft_package presumably containing the type declaration for complex is not present.
The declaration for signed_converted_input is also not present.
A sequential conditional signal assignment statement is only available in VHDL-2008.
There's a good argument to be made that the Synopsys packages std_logic_arith and std_logic_signed are not compatible with IEEE Std 1076-2008's defined package std_logic_1164. It's possible they've been re-written to accomidate the new definitions of std_logic_vector and std_ulogic vector, although not if they work without -2008 compatibility, without some serious automagic on the part of ALDEC.
If passing a -2008 compatibility flag doesn't fix things for you the simplest thing you can do is replace the sequential conditional signal assignment statement with two simple signal assignment statements inside an if statement:
library ieee;
use ieee.std_logic_1164.all;
-- use ieee.numeric_std.all;
use ieee.std_logic_arith.all;
package fft_package is
type complex is record
sig_real: signed (15 downto 0);
sig_imaginary: signed (15 downto 0);
end record;
constant signed_converted_input: signed (15 downto 0) := (others => '0');
end package;
library ieee;
use ieee.std_logic_1164.all;
-- use ieee.numeric_std.all;
use ieee.std_logic_arith.all;
use work.fft_package.all;
entity S8BT16B is
port(
clk_50: in std_logic;
clk_baud: in std_logic;
main_reset: in std_logic;
enable: in std_logic;
sig_in: in signed (7 downto 0);
sig_out: out complex;
valid_output: out std_logic
);
end S8BT16B;
architecture Behavioral of S8BT16B is
type state is (idle,start);
signal state_reg, next_state_reg: state;
signal sig_out_real: signed(15 downto 0);
begin
state_change:
process(clk_50, main_reset)
begin
if (main_reset = '1' or enable = '0') then
state_reg <= idle;
elsif (main_reset ='0' and enable = '1') then
state_reg <= next_state_reg;
end if;
end process;
S8BT16B_active:
process(clk_baud, state_reg)
begin
if state_reg = idle then
sig_out_real <= "0000000000000000";
sig_out <=(sig_out_real,"0000000000000000");
next_state_reg <= start;
valid_output <= '0';
elsif state_reg = start and enable = '1' then
-- sig_out_real <= X"00" & sig_in when sig_in(7)='0' else
-- X"ff" & sig_in;
if sig_in(7) = '0' then
sig_out_real <= X"00" & sig_in;
else
sig_out_real <= X"ff" & sig_in;
end if;
sig_out <= (signed_converted_input, "0000000000000000");
next_state_reg <= idle;
valid_output <= '1';
end if;
end process;
end Behavioral;
This code analyzes, elaborates and simulates (to show there are no length mismatches without regards to sig_in(7) = '0') while any claim to it's functionality is not made. The length looks right in the assignments to sig_out_real.
And of course without seeing the actual contents of your package fft_package claims to syntax and semantic validity can't be absolutely made (the faux package and your modified code are consistent with each other).
I have written 2 state machines in my VHDL code. The simulation works fine, but the code does not synthesize. Any help would be appreciated. Here is my code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_arith.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;
use IEEE.NUMERIC_STD.ALL;
entity pulse_width is
Port ( clk : in STD_LOGIC;
timer2:in std_logic;
input: in STD_LOGIC;
result: inout STD_LOGIC_VECTOR (15 downto 0);
SEL_LINE: IN STD_LOGIC_VECTOR(5 DOWNTO 0);
data_out: out STD_LOGIC_VECTOR (23 downto 0):=x"000000");
end pulse_width;
architecture Behavioral of pulse_width is
TYPE count_states is (s0,s0_dash,s1,s2,s3,s1_dash);
SIGNAL current_state, next_state : count_states := s0 ;
TYPE write_states is (ws0,ws0_dash,ws1,ws2,ws3,ws4);
SIGNAL current_state1, next_state1 : write_states := ws0 ;
TYPE index_array is ARRAY(integer range 0 to 65535) of std_logic_vector(15 downto 0);
SIGNAL mem: index_array;
SIGNAL count: std_logic_vector(15 downto 0):=x"0000";
SHARED VARIABLE j: integer:=0;
SHARED VARIABLE a,i: integer:=1;
SIGNAL flag,push_data,push_first,push_final,push_pulses,rw_first,rw_end: std_logic:='0';
SIGNAL y_clk_input ,y_clk_timer2, enable_count: std_logic:='0';
SIGNAL first,final: std_logic_vector(15 downto 0):= x"0001";
begin
-- Pulse width count
process (clk)
begin
if rising_edge(clk) then
current_state<=next_state;
current_state1<=next_state1;
end if;
end process;
process(input,SEL_LINE,current_state)
begin
------------------------------------------------------------------------
case current_state is
when s0 =>
if(input='1') then
next_state<=s1;
else
next_state<=s0;
end if;
when s1 =>
flag<='0';
if input='1' then
count <= count+ x"0001";
next_state<=s1_dash;
else
next_state<=s2;
end if;
when s1_dash =>
if input='1' then
count <= count+ x"0001";
next_state<=s1;
else
next_state<=s2;
end if;
when s2 =>
result <= count;
next_state<=s3;
when s3=>
count <= x"0000";
next_state<=s0;
enable_count<='0';
when others =>
next_state<=s0;
end case;
--------------------------------------------------------------------------
case current_state1 is
when ws0 =>
if (result>x"0000") then
next_state1<=ws1;
else
next_state1<=ws0_dash;
end if;
when ws0_dash =>
if (result>x"0000") then
next_state1<=ws1;
else
next_state1<=ws0;
end if;
when ws1=>
if rw_first='1' and rw_end='1' then
next_state1<=ws0;
else
mem(a) <= result;
a:=a+1;
final<=final+x"0001";
next_state1<=ws2;
end if;
when ws2 =>
next_state1<=ws0;
result<=x"0000";
when others =>
next_state1<=ws0;
end case;
end process;
I eventually need to implement three state machines.
The math you're trying to do in the asynchronous state logic is not registered and won't synthesize well. You need to re-arrange your state logic so statements like:
count <= count+ x"0001";
...
final<=final+x"0001";
...are synchronous and not 'free running' in an asynchronous loop.
The problem is that you read and write the same signals in one combinational process.
Either put everything in one clocked (synchronous) process
Or: use explicit registers: count_next <= count + x"0001";
Not related to your error, but still worth paying attention to:
You have a ton of unused signals and shared variables:
push_data,push_first,push_final,push_pulses, y_clk_input ,y_clk_timer2, first, i,j
This is confusing for anybody trying to read your code. 1
The packages STD_LOGIC_arith and STD_LOGIC_unsigned are deprecated