Why does this Full Adder Function not work VHDL - vhdl

Question

Library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity ALU is
port( A: in STD_LOGIC_VECTOR(7 downto 0);
B: in STD_LOGIC_VECTOR(7 downto 0);
C: in STD_LOGIC_VECTOR(3 downto 0);
Result: out STD_LOGIC_VECTOR(7 downto 0));
end ALU;
architecture arch of ALU is
----------------- SUM------------------------------------------------
function SUM (X:STD_LOGIC; Y:STD_LOGIC;CIN :STD_LOGIC) return STD_LOGIC is
variable Res: STD_LOGIC;
begin
Res:= X XOR Y XOR CIN;
return Res;
end SUM;
function Carry(X:STD_LOGIC; Y:STD_LOGIC;CIN :STD_LOGIC) return STD_LOGIC is
variable Res: STD_LOGIC;
begin
Res:=(X AND Y) OR (CIN AND X) OR (CIN AND Y);
return Res;
end Carry;
------------------------------------------------------------------
function Adder(A:STD_LOGIC_VECTOR;B :STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
variable Res: STD_LOGIC_VECTOR(0 to 7);
variable Car: STD_LOGIC_VECTOR(0 to 8);
begin
Car(0):='0';
for i in 0 to 7 loop
Res(i):=SUM(A(i),B(i),Car(i));
Car(i+1):= Carry(A(i),B(i),Car(i));
end loop;
return Res;
end Adder;
begin
Result <= Adder("00110010","00000010");
end arch;
Hello I am a bit confused on why this full adder function does not work. I have tried multiple times to fix it however it does not give the correct output.
I am unsure where the errors are in the sum or carry or adder function. I do not know what to do to ensure it works. I also do not want to make a different component for a full adder.