I am writing code in VHDL in which a number is multiplied by a vector. But it gives an error.
Library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity multi is
port ( clk : in std_logic;
ipixel : in std_logic_vector(15 downto 0);
opixel : out std_logic_vector(15 downto 0)
);
end entity multi;
architecture rtl of multi is
begin
process (clk) begin
if rising_edge (clk) then
opixel (15 downto 11) <= std_logic_vector(unsigned(ipixel(15 downto 11))*3);
opixel (10 downto 5) <= std_logic_vector(unsigned(ipixel(10 downto 5))* 3);
opixel (4 downto 0) <= std_logic_vector(unsigned(ipixel(4 downto 0))* 3);
end if;
end process;
end architecture rtl;
The error is:
Target slice 5 elements; Value is 10 elements
When you multiply an unsigned value with a natural, this is defined in NUMERIC_STD as follows:
function "*" (L: UNSIGNED; R: NATURAL) return UNSIGNED is
begin
return L * TO_UNSIGNED(R, L'LENGTH);
end "*";
Return value will result in 2 * length of your unsigned factor!
Related
I have my simple code in VDHL that seperates digit from 2-digit number, but when testing, my seperated digits remain unsigned (u).
I have a hunch that the problem may be in the types of variables, when I use operations on them that they do not support.
I use ghdl with gtkwave Variables in gtkwave
--FULL LOGIC--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity DigitSeparator is
port(
value: in unsigned(6 downto 0);
leastSingnificantDigit: out unsigned(3 downto 0);
mostSignificantDigit: out unsigned(3 downto 0)
);
end entity DigitSeparator;
architecture DigitSeparator of DigitSeparator is
begin
-- Set the outputs to 1111 1111 if the input is greater than 99
process(value)
begin
if value > 99 then
leastSingnificantDigit <= "1111";
mostSignificantDigit <= "1111";
else
leastSingnificantDigit <= value mod 10;
mostSignificantDigit <= value / 10;
end if;
end process;
end architecture DigitSeparator;
--TEST BENCH--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity DigitSeparatorTB is
end entity DigitSeparatorTB;
architecture DigitSeparatorTB of DigitSeparatorTB is
component DigitSeparator
port(
value: in unsigned(6 downto 0);
leastSingnificantDigit: out unsigned(3 downto 0);
mostSignificantDigit: out unsigned(3 downto 0)
);
end component DigitSeparator;
signal value: unsigned(6 downto 0) := "0110000";
signal leastSingnificantDigit: unsigned(3 downto 0);
signal mostSignificantDigit: unsigned(3 downto 0);
begin
kaka: DigitSeparator port map (value, leastSingnificantDigit, mostSignificantDigit);
value <= "0110000", "1111111" after 100 ns, "1000010" after 200 ns;
end architecture DigitSeparatorTB;
The problem is when I try to assign a 4 bit variable (leastSingnificantDigit, mostSignificantDigit) a result that has 7 bits, so I have to guarantee that the result will only have 4 bits thanks to the parenthesis "3 downto 0"
This works:
leastSignificantDigit <= "mod" (value, 10)(3 downto 0);
mostSignificantDigit <= "/" (value, 10)(3 downto 0);
I have a Problem. I have an array of std_logic_vector and I input a value unsinged(3 downto 0) and I want to use value as the Index of the array.
So far so good but I should get a std_logic_vector out of the array and put in the Output segments (which is also a std_logic_vector with the same size) but I get the error:
> can't match type conversion with type array type "std_logic_vector"
here is my Code:
> library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity getarrayvalue is
port(
value : in unsigned(3 downto 0);
clk : in std_logic;
segments : out std_logic_vector(6 downto 0)
);
end entity;
architecture v1 of getarrayvalue is
type rom_type is array(0 to 9) of std_logic_vector(6 downto 0);
signal rom: rom_type :=("1111110","0110000","1101101","1111001","0110011","1011011","1011111","1110000","1111111","1111011");
signal val_i: integer;
val_i <= to_integer(value);
process(clk)
begin
if rising_edge(clk) then
segments <= rom_type(val_i);
end if;
end process;
end architecture;
Does anyone know how to fix this problem ? Thanks!
I have code designed for Vivid software. How I can translate this code into ModelSIM? In vivado, I should get the following values, but in modelsim I get completely different ones.
This is noise generator. Successful in adding pseudorandom noise sequence to our sine wave, but now we are trying to add Gaussian noise. The code and the simulation results for ADDITION OF PSEUDORANDOM NOISE SEQUENCE TO SINE WAVE IS GIVEN BELOW:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL; --try to use this library as much as possible.
entity sine_wave is
generic ( width : integer := 4 );
port (clk :in std_logic;
random_num : out std_logic_vector (width-1 downto 0);
data_out : out STD_LOGIC_VECTOR(7 downto 0)
);
end sine_wave;
architecture Behavioral of sine_wave is
signal data_out1,rand_temp1,noisy_signal : integer;
signal noisy_signal1 : STD_LOGIC_VECTOR(7 downto 0);
signal i : integer range 0 to 29:=0;
--type memory_type is array (0 to 29) of integer;
type memory_type is array (0 to 29) of std_logic_vector(7 downto 0);
--ROM for storing the sine values generated by MATLAB.
signal sine : memory_type := ("01001101","01011101","01101100","01111010","10000111","10010000","10010111","10011010","10011010");
--hi
begin
process(clk)
variable rand_temp : std_logic_vector(width-1 downto 0):=(width-1 => '1',others => '0');
variable temp : std_logic := '0';
begin
--to check the rising edge of the clock signal
if(rising_edge(clk)) then
temp := rand_temp(width-1) xor rand_temp(width-2);
rand_temp(width-1 downto 1) := rand_temp(width-2 downto 0);
rand_temp(0) := temp;
--data_out <= sine(i);
i <= i+ 1;
if(i = 29) then
i <= 0;
end if;
end if;
data_out <= sine(i);
data_out1<=to_integer(unsigned(sine(i)));
random_num <= rand_temp;
rand_temp1<=to_integer(unsigned(rand_temp));
noisy_signal<=data_out1+rand_temp1;
noisy_signal1<= std_logic_vector(to_signed(noisy_signal,8));
end process;
end Behavioral;
Vivado
ModelSIM
I am writing Bin to BCD code Multiplier and in the top module Xilinx ISE gives this error:
Line 30: found '0' definitions of operator "+", cannot determine exact
overloaded matching definition for "+"
while I have mapped the ports to the top module
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
-- library UNISIM;
-- use UNISIM.VComponents.all;
entity EightDisplayControl is
Port ( clk : in STD_LOGIC;
leftL, near_leftL : in STD_LOGIC_VECTOR (3 downto 0);
near_rightL, rightL : in STD_LOGIC_VECTOR (3 downto 0);
leftR, near_leftR : in STD_LOGIC_VECTOR (3 downto 0);
near_rightR, rightR : in STD_LOGIC_VECTOR (3 downto 0);
select_display : out STD_LOGIC_VECTOR (7 downto 0);
segments : out STD_LOGIC_VECTOR (6 downto 0));
end EightDisplayControl;
architecture Behavioral of EightDisplayControl is
signal Display : std_logic_vector(2 downto 0);
signal div : std_logic_vector(16 downto 0);
signal convert_me : std_logic_vector(3 downto 0);
begin
div<= div+1 when rising_edge(clk);
Display <= div(16 downto 14);
process(Display, leftL, near_leftL, near_rightL, rightL, leftR, near_leftR, near_rightR, rightR)
begin
if Display ="111" then select_display <= "11111110"; convert_me <= leftL;
elsif Display ="110" then select_display <= "11111101"; convert_me <= near_leftL;
elsif Display ="101" then select_display <= "11111011"; convert_me <= near_rightL;
elsif Display ="100" then select_display <= "11110111"; convert_me <= rightL;
elsif Display ="011" then select_display <= "11101111"; convert_me <= leftR;
elsif Display ="010" then select_display <= "11011111"; convert_me <= near_leftR;
elsif Display ="001" then select_display <= "10111111"; convert_me <= near_rightR;
else select_display <= "01111111"; convert_me <= rightR;
end if;
end process;
decoder : entity work.segment_decoder
port map (convert_me, segments);
end Behavioral;
As has already been stated in comments, the problem is that you have defined signal div as a std_logic_vector. The IEEE.numeric_std library does not define an addition operation for std_logic_vector.
Looking in the library we see:
--============================================================================
-- Id: A.3
function "+" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(MAX(L'LENGTH, R'LENGTH)-1 downto 0).
-- Result: Adds two UNSIGNED vectors that may be of different lengths.
-- Id: A.4
function "+" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(MAX(L'LENGTH, R'LENGTH)-1 downto 0).
-- Result: Adds two SIGNED vectors that may be of different lengths.
-- Id: A.5
function "+" (L: UNSIGNED; R: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0).
-- Result: Adds an UNSIGNED vector, L, with a non-negative INTEGER, R.
-- Id: A.6
function "+" (L: NATURAL; R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(R'LENGTH-1 downto 0).
-- Result: Adds a non-negative INTEGER, L, with an UNSIGNED vector, R.
-- Id: A.7
function "+" (L: INTEGER; R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(R'LENGTH-1 downto 0).
-- Result: Adds an INTEGER, L(may be positive or negative), to a SIGNED
-- vector, R.
-- Id: A.8
function "+" (L: SIGNED; R: INTEGER) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0).
-- Result: Adds a SIGNED vector, L, to an INTEGER, R.
--============================================================================
This clearly shows that only functions for adding unsigned, signed, natural, and integer are supported.
As #Tricky has stated in the comments, you need to define div as an unsigned.
I was writing a code in vhdl (xilinx) for a digital tachometer.
While converting the std_logic_vector m1 to integer the following errors were shown by the compiler.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
entity tacho is
Port ( A : in STD_LOGIC;
B : out STD_LOGIC_vector (15 downto 0));
end tacho;
architecture Behavioral of tacho is
component counter
port(
clk: in std_logic;
m: out std_logic_vector (4 downto 0));
end component;
signal m1 : std_logic_vector (4 downto 0);
variable y: integer := 0;
variable z: integer := 0;
begin
x: counter port map(A,m1);
y:= to_integer(unsigned(m1)); --error1:Syntax error near ":=". error2:Expecting type void for <to_integer>.
z:= y * 60; --Syntax error near ":=".
B <= std_logic_vector(to_unsigned(z, 16));
end Behavioral;
I found in many websites that the syntax i wrote is correct.
Please help!
Variables y and z can't be declared at architecture level. Use signals instead, and the signal assign <=, like:
...
signal y : integer;
signal z: integer := 0;
begin
x: counter port map(A, m1);
y <= to_integer(unsigned(m1));
z <= y * 60;
B <= std_logic_vector(to_unsigned(z, 16));
...
Or simply combine it and avoid the intermediates y and z, like:
...
x: counter port map(A, m1);
B <= std_logic_vector(resize(60 * unsigned(m1), B'length));
...
A non-shared variable can only be declared in a process statement or subprogram. You could place your scaling code in a process:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tacho is
port ( A: in std_logic;
B: out std_logic_vector (15 downto 0)
);
end entity tacho;
architecture behavioral of tacho is
component counter is
port (
clk: in std_logic;
m: out std_logic_vector (4 downto 0)
);
end component;
signal m1 : std_logic_vector (4 downto 0);
begin
x: counter port map (A, m1);
scaling:
process (m1)
variable y: integer := 0;
variable z: integer := 0;
begin
y := to_integer(unsigned(m1));
z := y * 60;
B <= std_logic_vector(to_unsigned(z, 16));
end process;
end architecture behavioral;
Or you could move your calculations to a subprogram:
architecture scaled of tacho is
component counter is
port (
clk: in std_logic;
m: out std_logic_vector (4 downto 0)
);
end component;
signal m1 : std_logic_vector (4 downto 0);
function scale(m1: std_logic_vector (4 downto 0); SIZE: natural := 16)
return std_logic_vector is
variable y: integer;
variable z: integer;
begin
y := to_integer(unsigned(m1));
z := y * 60;
return std_logic_vector(to_unsigned(z, SIZE));
end function;
begin
x: counter port map (A, m1);
scaled_output:
B <= scale(m1);
end architecture;
Both of these analyze.