Quartus netlist optimization lost register fanout in a state machine - vhdl

Question

Hi guys i'm trying to implement a state machine but i have the problem that during timing simulation i get an error saying that
Info: 1 registers lost all their fanouts during netlist optimizations. The first 1 are displayed below.
Info: Register "state.STATE_I" lost all its fanouts during netlist optimizations.
and in the waveform timing simulation the output works fine but if i try to check the actual state I only get an initial state (STATE I) and an "UNDEFINED" in the rest of places where the actual state should be shown, the code is:
library ieee;
use ieee.std_logic_1164.all;
--define entity
entity pregunta1a is
port(
resetn : in std_logic;
clock : in std_logic;
w : in std_logic;
z : out std_logic
);
end pregunta1a;
--define architecture
architecture behavior of pregunta1a is
type STATE_TYPE is (STATE_A,STATE_B,STATE_C,STATE_D,STATE_E,STATE_F,STATE_I); -- todos los estados
signal state, next_state : STATE_TYPE;
begin
process(clock)
begin
if(rising_edge(clock)) then
if (resetn='0') then
state <= STATE_I;
else
state <= next_state;
end if;
end if;
end process;
process(state,w) -- complete sensitivity list
begin
z<='0';
case state is
when STATE_A =>
if (w = '1') then
next_state <= STATE_B;
else
next_state <= STATE_C;
end if;
when STATE_B =>
if (w = '1') then
next_state <= STATE_D;
else
next_state <= STATE_A;
end if;
when STATE_C =>
if (w = '1') then
next_state <= STATE_B;
else
next_state <= STATE_E;
end if;
when STATE_D =>
if (w = '1') then
next_state <= STATE_F;
else
next_state <= STATE_A;
end if;
when STATE_E =>
if (w = '1') then
next_state <= STATE_B;
else
next_state <= STATE_E;
z<='1';
end if;
when STATE_F =>
if (w = '1') then
next_state <= STATE_F;
z<='1';
else
next_state <= STATE_A;
end if;
when STATE_I =>
if (w = '1') then
next_state <= STATE_B;
else
next_state <= STATE_A;
end if;
end case;
end process;
end behavior;
This is a screenshot of the timing simulation
anyone known how to solve this ??

Answer 1

i´ve found a solution to my problem, it seems that i have to force some type of interaction with the register lost (state_I). I've changed some parts of the code and ordered it to make things more clear:
library ieee;
use ieee.std_logic_1164.all;
--define entity
entity pregunta1a is
port(
resetn : in std_logic;
clock : in std_logic;
w : in std_logic;
z : out std_logic
);
end pregunta1a;
--define architecture
architecture behavior of pregunta1a is
type STATE_TYPE is (STATE_A,STATE_B,STATE_C,STATE_E,STATE_F,STATE_G,STATE_R); -- todos los estados
signal state, next_state : STATE_TYPE:=state_R;
begin
process(clock)
begin
if(rising_edge(clock)) then
if (resetn='0') then
state <= STATE_R;
else
state <= next_state;
end if;
end if;
end process;
process(state,w,resetn) -- complete sensitivity list
begin
z<='0';
next_state<=state_R;
case state is
when STATE_A =>
if (w = '0') then
next_state <= STATE_B;
else
next_state <= STATE_E;
end if;
when STATE_B =>
if (w = '0') then
next_state <= STATE_C;
else
next_state <= STATE_E;
end if;
when STATE_C =>
if (w = '0') then
next_state <= STATE_C;
z<='1';
else
next_state <= STATE_E;
end if;
when STATE_E =>
if (w = '0') then
next_state <= STATE_A;
else
next_state <= STATE_F;
end if;
when STATE_F =>
if (w = '0') then
next_state <= STATE_A;
else
next_state <= STATE_G;
end if;
when STATE_G =>
if (w = '0') then
next_state <= STATE_A;
else
next_state <= STATE_G;
z<='1';
end if;
when STATE_R =>
if(resetn='1') then
if (w = '0') then
next_state <= STATE_A;
else
next_state <= STATE_E;
end if;
else
next_state<=state_R;
end if;
end case;
end process;
end behavior;
it seems that i have to force some type of interaction to establish STATE_I, the programs was working as it was, but one of the requirements was to get rid of this problem in the simulation