Vhdl Parallel or Serial-in/ Parallel-out register - vhdl

Question

I want to build a n bits register which can take both serial or parallel input depending of a bit SERIAL. And always parallel output. See my code below. My issue is that I need to use a If statement to choose my input (parallel or serial) (which must be inside a process) and I also need a for generate statement because I work with generic n bit register (which cannot be done inside a process) to build the n D-Flipflop.
I was thinking to use for loop instead of for i ..generate but I need to use that i as index.
Does anyone know how to fix my code? The main issue is that using serial input, the flipflop are connected in series while parallel input, the flipflops are independent. And I don't know how to model that proprely.
Thank you
-- Parallel or Serial-in / Parallel-out n bits register
library ieee;
use ieee.std_logic_1164.all;
entity PSIPOreg is
generic(n: integer);
port(RST, Clk_reg, enable, SERIAL: in std_logic;
Din_P: in std_logic_vector(n-1 downto 0);
Din_S: in std_logic;
Qout: out std_logic_vector(n-1 downto 0));
end PSIPOreg;
architecture bhv of PSIPOreg is
component D_FlipFlop
port(D, Clk, reset, EN : in std_logic;
Q : out std_logic);
end component;
signal parallel_data : std_logic_vector(0 to n-1) := (others =>'0');
signal temp_input: std_logic_vector(0 to n-1) := (others =>'0');
begin
Qout <= parallel_data;
process(SERIAL, Clk_reg, enable, RST)
begin
if(SERIAL = '0') then -- PIPO register
temp_input <= Din_P;
gen_reg: for i in 0 to n-1 generate
regx: D_FlipFlop port map(D => temp_input(i), Clk => Clk_reg, reset => RST, EN => enable, Q => Qout(i));
end generate gen_reg;
elsif(SERIAL = '1') then -- SIPO register
temp_input(0) <= Din_S;
shift_reg: for i in 0 to n-1 generate
begin
dff_lsb: if i = 0 generate
begin
dff: D_FlipFlop port map(D => temp_input(0), Clk => Clk_reg, reset => RST, EN => enable, Q => parallel_data(i));
--Qout(i) <= parallel_data(i);
end generate dff_lsb;
dff_mid: if((i>0) and (i<(n-1))) generate
begin
dff: D_FlipFlop port map(D => parallel_data(i-1), Clk => Clk_reg, reset => RST, EN => enable, Q => parallel_data(i));
--Qout(i) <= parallel_data(i);
end generate dff_mid;
dff_msb: if i = n-1 generate
begin
dff: D_FlipFlop port map(D => parallel_data(i-1), Clk => Clk_reg, reset => RST, EN => enable, Q => Qout(i));
end generate dff_msb;
end generate shift_reg;
end if;
end process;
end bhv;