Problem when passing argument to Makefile - bash

Question

My Makefile looks like this:
OBJ = $(SRC:.c=.c.o) #yes it it should be renamed to .c.o, not .o
LIBS = -lchecl -lchecs -lchengine-dev -lglfw -lm -lGL -lGLEW -lcheio -lopenal -lfreetype
EXE = test
VER = -std=c99
MODE = -g
OPT = -O0
ERR = -Wall -Wuninitialized -Werror=implicit-function-declaration -Wextra -Wno-unused-parameter -Wno-incompatible-pointer-types -Werror=int-conversion -Wduplicated-cond -Wlogical-op -Wrestrict -Wnull-dereference -Wjump-misses-init -Wdouble-promotion -Wshadow -Wformat=2
LFLAGS = -o
CFLAGS = $(ERR) $(VER) $(OPT) -c $(MODE) `pkg-config --cflags freetype2`
run: $(EXE)
./$(EXE)
$(EXE): $(OBJ)
gcc $(LFLAGS) $(EXE) $(OBJ) $(LIBS)
%.o: %.c
gcc -c $(CFLAGS) $*.c
mv "$$(basename $*.o)" "$$(dirname $*)"
cleanall:
rm $(OBJ)
rm $(SRC)
And I am passing the SRC variable like this:
files=$(find . -type f -name '*.c.c')
make run SRC="$files"
But this gives the the following error:
make: *** No rule to make target 'src/setup.c
./states/mainMenuState.c
...
(a list of all source files)'
However if I manually copy the value of $files into the Makefile, writing SRC = and then the source files, it compiles just fine. If I write instead of OBJ = $(SRC:.c.c=.c.o) OBJ = $($(SRC):.c.c=.c.o) it seems to compile but not link correctly, because then I get this error:
//usr/local/lib/libchengine-dev.so: undefined reference to `vector_find'
//usr/local/lib/libchengine-dev.so: undefined reference to `che_init'
//usr/local/lib/libchengine-dev.so: undefined reference to `vector_destruct'

Answer 1

SRC is used in the definition of OBJ. But this can't be your real makefile, because it won't work. So something must be different about your real makefile versus what you've shown us, and that difference is critical to the problem you're having. As Renaud says, please provide a MCVE.
I created a simple makefile:
OBJS := $(SRC:.c=.c.o)
all: $(OBJS)
%.c.o : %.c
: $< $#
then ran it:
files=$(find -name \*.c)
make SRC="$files"
and it worked just fine:
: foo.c foo.c.o
: bar.c bar.c.o
: biz.c biz.c.o
: baz.c baz.c.o
You can work around the problem in GNU make 4.1 by not including newlines in the $files variable. For example you can change how you set it to this:
files=$(find . -type f -name '*.c.c' -printf '%p ')
so it uses space separators instead of newlines.