I am trying to implement a PID controller using Verilog, but I faced some problems in the coding.
I try to set the position as a parameter like shown in the screens shot:
but, I faced an error which I am not aware of:
Error1:-
Error (10170): Verilog HDL syntax error at Verilog1.v(16) near text: "["; expecting an operand. Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
Error2:-
Error (10170): Verilog HDL syntax error at Verilog1.v(34) near text: "["; expecting "#", or an operand. Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
I also tried the like integer position= [0*IRL+1000*CIR+2000*IRR];, but still, I face the same problem. How do I fix this syntax error?
After compiling, parameter values can only be read; not modified. They are runtime constants. An integer type can only be assigned within an procedural block. You can give it an initial value at declarations, but it will not auto update. So you want a procedure assignment or a net type with continuous assignment.
Square brackets ([]) are used for indexing an array or slice of a vector. They cannot be used like parentheses (()) or curly brackets ({}). In your case non are needed.
Change:
integer position= [0*IRL+1000*CIR+2000*IRR];
To:
wire [31:0] position= 0*IRL+1000*CIR+2000*IRR;
Or:
wire [31:0] position;
assign position= 0*IRL+1000*CIR+2000*IRR;
Or:
integer position;
always #* begin
position= 0*IRL+1000*CIR+2000*IRR;
end
Also change:
Proportional<= [position/IRL+CIR+IRR]-1000;
To:
Proportional<= (position/IRL+CIR+IRR)-1000;
Assuming IRL, CIR and IRR are declared as constant type (like parameter), then you should remove the square brackets:
parameter position = 0*IRL+1000*CIR+2000*IRR;
Related
I have an hierarchy created by a for-generate like this:
INST: for ... generate
. . .
end generate;
It creates many instances, as expected, named as INST__0, INST__1, etc, which names have a double underscore on it.
When I try to create an alias to a signal A in this hierarchy I got an error like "Invalid literal" because the path to the signal has double underscores, which is indeed invalid in VHDL:
alias A is <<signal DUT.INST__0.COUNTER.A: std_logic>>;
Is there any way to solve this problem? Prevent for-generate using double underscores, maybe?
Thanks
You do not provide a reproducible or complete example nor demonstrate the syntax location of your alias declaration. Particular note the lack of a the loop parameter which your attempt alludes to include values 0 and 1.
See IEEE Std 1076-2008 8.7 External names
pathname_element ::=
entity_simple_name
| component_instantiation_label
| block_label
| generate_statement_label [ ( static_expression ) ]
| package_simple_name
and the accompanying semantic description of the the static expression:
b)Second, for each package simple name in a package pathname, or for each pathname element in an absolute or relative pathname, in order, the previously identified declarative region is replaced as the identified declarative region by one of the following:
...
5)For a generate statement label, the declarative region of the equivalent block corresponding to the generate statement. If the generate statement is a for generate statement, the pathname element shall include a static expression, the type of the expression shall be the same as the type of the generate parameter, and the value of the expression shall belong to the discrete range specified for the generate parameter. The type of the expression shall be determined by applying the rules of 12.5 to the expression considered as a complete context, using the rule that the type shall be discrete. If the type of the expression is universal_integer and the type of the generate parameter is an integer type, an implicit conversion of the expression to the type of the generate parameter is assumed.
We see that the static expression included in parentheses following the generate statement label is a value of the loop parameter.
A -2008 example that can be analyzed, elaborated and simulated:
entity for_gen_label is
end entity;
architecture fum of for_gen_label is
begin
INST:
for i in 0 to 3 generate
COUNTER:
block
signal a: boolean;
begin
PROC_LABEL:
process
begin
report a'INSTANCE_NAME;
wait;
end process;
end block;
end generate;
end architecture;
where we also see that the -2008 predefined attribute 'INSTANCE_NAME can also demonstrate path name elements (GHDL):
for_gen_label.vhdl:16:17:#0ms:(report note): :for_gen_label(fum):inst(0):counter:a
for_gen_label.vhdl:16:17:#0ms:(report note): :for_gen_label(fum):inst(1):counter:a
for_gen_label.vhdl:16:17:#0ms:(report note): :for_gen_label(fum):inst(2):counter:a
for_gen_label.vhdl:16:17:#0ms:(report note): :for_gen_label(fum):inst(3):counter:a
The format of the 'INSTANCE_NAME predefined attribute value is given in 16.2.5 Predefined attributes of named entities.
The two underscores is a C(++) affectation for names which indicates you're probably getting information from the user interface of a simulator capable of supporting multiple hardware description languages. GHDL, a batch simulator supporting only VHDL produces output that adheres to VHDL path name elements:
ghdl -r for_gen_label --disp-signals-map
.for_gen_label(fum).inst(0).counter.a: 00007FBDBD504700 net: 0
.for_gen_label(fum).inst(1).counter.a: 00007FBDBD5047A0 net: 0
.for_gen_label(fum).inst(2).counter.a: 00007FBDBD504840 net: 0
.for_gen_label(fum).inst(3).counter.a: 00007FBDBD5048E0 net: 0
...
while incidentally demonstrating the entire path. VHDL unlike some other HDL's is not identifier case sensitive.
I would try an extended identifier. I would try both of the following, but I suspect the first one will get you there (and the second one not):
alias A is <<signal DUT.\INST__0\.COUNTER.A : std_logic>>;
and
alias A is <<signal \DUT.INST__0.COUNTER.A\ : std_logic>>;
I am concerned though the second one would be seen as a single identifier.
Can somebody explain what this naming convention means in the Verilog line below?
I don't know what this \add_34/.... part means?
ADDHXL \add_34/U1_1_6 (.A(n1022),.B(\add_34/carry[6] ),.CO(\add_34/carry[7] ),.S(N11));
If I have a wire named \add_34/carry[6] in my definition, should I have \add_34/carry[1] up to \add_34/carry[5], or is it optional?
I asked this question since compiling a part of my code, I get this syntax error:
Syntax error at or near token 'wire'.
Here is the code snippet:
RandomDelay R00001(clk,rst_n,2'b10,a34_carry_pri_delayed_7,\add_34/carry[7]);
wire N11_pri_delayed;
And here is module defintion:
module RandomDelay ( clk, reset_not, seed, input_signal, delayed_signal );
input [1:0] seed;
input clk, reset_not, input_signal;
output delayed_signal;
....
It is called an 'escaped identifier'.
When an identifier starts with a backslash, every character except white space is assumed to be part of the name. (Thus the standard identifier rules go out the window.)
Thus the identifier in your case is "\add_34/U1_1_6". Identifiers of that type are normally generate by a program.
Thus this is a valid identifier: \wow!/neverseen[]thissort#;of#++mess
Let's have a look at the identifier: \add_34/carry[6]. Note that the "[6]" is NOT an index! Is is seen as ASCII and part of the name.
The same again for \add_34/carry[7].
It also means somewhere there is a definition which goes:
wire \add_34/carry[6] ;
wire \add_34/carry[7] ;
// Note the space ^ before the semicolon!
The other \add_34/carry[... variables may exist or not as we are all looking at individual wires here.
It is perfectly legal for there to be no \add_34/carry[5] or \add_34/carry[0]
Coming back to your code:
RandomDelay R00001(clk,rst_n,2'b10,a34_carry_pri_delayed_7,\add_34/carry[7]);
You must thus place a space before the closing bracket:
RandomDelay R00001(clk,rst_n,2'b10,a34_carry_pri_delayed_7,\add_34/carry[7] );
// ---->>> Here ^
I am learning OCaml and I'm a complete beginner at this point. I'm trying to get used to the syntax and I just spent 15 minutes debugging a stupid syntax error.
let foo a b = "bar";;
let biz = foo 2. -1.;;
I was getting an error This expression has type 'a -> string but an expression was expected of type int. I resolved the error, but it prompted me to learn what is the best way to handle this syntax peculiarity.
Basically OCaml treats what I intended as the numeric constant -1. as two separate tokens: - and 1. and I end up passing just 1 argument to foo. In other languages I'm familiar with this doesn't happen because arguments are separated with a comma (or in Scheme there are parentheses).
What is the usual way to handle this syntax peculiarity in OCaml? Is it surrounding the number with parentheses (foo 2. (-1.)) or there is some other way?
There is an unary minus operator ~-. that can be used to avoid this issue: foo ~-.1. (and its integer counterpart ~-) but it is generally simpler to add parentheses around the problematic expression.
I'm getting (fairly reguarly) an "Error 16: Expression too complex" runtime error on a simple assigment to a property from a class.
public property PropertyName() as double
PropertyName = mvarPropertyName
end property
The debug window points to the crash being on the assignment line in the above code.
Some inital reading here and elsewhere suggested that it was related to the line calling the property. However, that now looks like this:
variableName = ObjectName.PropertyName
And all arithmetic is done with variableName.
Even more oddly, if I just hit debug, then resume/F5 immediatley, everything is fine.
Trying to use the error handling code to do this doesn't seem to have worked however.
Any ideas what is causing this error?
Stop using Not (Not MyArray) to test for uninitialized arrays. This uses a bug in the compiler that has a known side effect of destabilizing the run-time leading to "Expression too complex" on random places.
VB6 - Returning/Detecting Empty Arrays is fairly complete thread on different ways to test for empty and uninitialized arrays.
A string expression is too complicated. Strings not assigned to variables (such as those returned by functions) are assigned to temporary locations during string expression evaluation. Having a large number of these strings can cause this error. Try assigning these strings to variables and use the variables in the expression instead.
I am having a little problem here. In the code below is a function that has two arguments when I attempt to execute the functions i obtained this error
Undefined function or method for input
arguments of type 'double' (X,CX) as shown in (1).
the function is coded as below
[CX,sse]= (vgg_kmiter(X, CX)) ....(1)
can someone point me out where is the problem with this code?
note that the x is the input points in a columns which is integer and the CX is the center of clustering which is also integer.
Thank you
[CX,sse]= (vgg_kmiter(X, CX)) ....(1)
Is not a valid line of code.
[CX,sse]= (vgg_kmiter(X, CX));
is fine, though the outer parentheses aren't needed.
[CX,sse]= (vgg_kmiter(X, CX)) %....(1)
is fine as well - everything after the % sign is considered a comment