VHDL State machie is skipping state - vhdl

Question

I have written FSM on a FPGA, when I run simulation using iSim everything looks good, problem starts when I run my program on board(I'm using Spartan SP605 Eval Kit), and after looking up on signals using chipscope, I discovered that it skips state when the ADV signal should be low (see code below) and it just follows thru that state to the next one on witch it is stuck.
I've check and I do not violate any of my timing requirement.
A little bit of my project:
I'm using Cypres board to receive and sent data to/from PC,hardware there works as it should be. This board is connected to FPGA via FMC interconnection board (also from Cypress). This board contains two buffers (FIFO; one for transfer to FPGA and one to transfer from FPGA), FPGA sees flags that indicates state of those buffers (flag A - full, B - partial full, C - empty, D - partial empty). FPGA is configured as loopback, it first reads all data from board, then transfer those data to it.
flags are active low.
I tried to force it to run without those if's (every clock cycle is new state), and it worked as expected (I got error from board that says it tries to read from empty buffer)
here is fragment of my State machie code, the state it skips is named ADDRRead.
If you are intrested in full code I posted it on pastebin https://pastebin.pl/view/ae9b57ce
process(currentFPGAMode, writeEnable, chipEnable, outputEnable, rdy, flagA, flagb, flagD, flagC, readEmptyDelayCnt, writeFullDelayCnt)
begin
case currentFPGAMode is
when Idle =>
if (flagc = '1') --check if buffer is avaible
then
nextFPGAMode <= waitFlagD;
else
nextFPGAMode <= Idle;
end if;
when waitFlagD =>
--wait for data to appear in buffer (from PC)
if (flagD = '1')
then
nextFPGAMode <= ADDRRead;
else
nextFPGAMode <= waitFlagD;
end if;
when ADDRRead =>
--setting up address bus to point on endpoint for read transfer
nextFPGAMode <= OeDelay;
when OeDelay =>
--waiting for valid data
if (rdy = '1')
then
nextFPGAMode <= FPGARead;
else
nextFPGAMode <= OeDelay;
end if;
when FPGARead =>
--valid data data are avaible here
if (flagD = '1') --check if there are data to be read
then
nextFPGAMode <= FPGARead;
else
nextFPGAMode <= ReadEndDelay;
end if;
when ReadEndDelay =>
if (readEmptyDelayCnt = 0)
then
nextFPGAMode <= FPGAReadEnd;
else
nextFPGAMode <= ReadEndDelay;
end if;
when FPGAReadEnd =>
--end read sequence
nextFPGAMode <= waitFlagA;
when waitFlagA =>
--checking if DMA Buffer is empty
if (flagA = '1')
then
nextFPGAMode <= ADDRWrite;
else
nextFPGAMode <= waitFlaga;
end if;
when ADDRWrite =>
--seting address bus to point at endpoint for writetransfer (address line = 3)
nextFPGAMode <= WeDelay;
when WeDelay =>
--waiting for valid data to apear
if (rdy = '1')
then
nextFPGAMode <= FPGAWrite;
else
nextFPGAMode <= WeDelay;
end if;
when FPGAWrite =>
--data are avaible to apear
if ( flagb = '0')
then
nextFPGAMode <= WriteEndDelay;
else
nextFPGAMode <= FPGAWrite;
end if;
when WriteEndDelay =>
if (writeFullDelayCnt = 0)
then
nextFPGAMode <= RDYDelay;
else
nextFPGAMode <= WriteEndDelay;
end if;
when RDYDelay =>
--Delay for rdy signal to deassert after finishing transfer
if (rdy = '0')
then
nextFPGAMode <= Idle;
else
nextFPGAMode <= RDYDelay;
end if;
when others =>
nextFPGAMode <= Idle;
end case;
end process;