This is the Makefile that I'm using for cross-buildig a kernel module.
export CROSS_COMPILE:=aarch64-none-linux-gnu-
export ARCH:=arm64
obj-m += chr_drv_ex1.o
export KDIR:=linux-source-5.4.0
#EXTRA_CFLAGS=-I../../qemu-5.1.0/hw/misc
#ccflags-y=-I../../qemu-5.1.0/hw/misc
all: test_chr_drv map_hugetlb test_ioctl_drv
make ARCH=$(ARCH) CROSS_COMPILE=$(CROSS_COMPILE) -C $(KDIR) M=$(PWD) modules
clean:
make ARCH=$(ARCH) CROSS_COMPILE=$(CROSS_COMPILE) -C $(KDIR) M=$(PWD) clean
rm -f test_chr_drv map_hugetlb test_ioctl_drv
%: %.c
$(CROSS_COMPILE)gcc $^ -o $#
Now in my chr_drv_ex1.c file, I want to include a header file placed in ../../qemu-5.1.0/hw/misc directory. What is the correct method to add this path? I saw this and tried setting EXTRA_CFLAGS and ccflags-y but none of them works(those are commented out above). Of course if I use #include "../../qemu-5.1.0/hw/misc/axpu_regs.h" in the chr_drv_ex1.c source I can compile it. But I want to use #include <axpu_regs.h>.
I changed the ccflags-y from
ccflags-y := -I../../qemu-5.1.0/hw/misc
to
ccflags-y := -I../../../qemu-5.1.0/hw/misc
So the include path should be specified as seen from the kernel make directory (where the Makefile for linux kernel is located. in this case linux-source-5.4.0 directory which is one step below from where I am now).
Related
I have a kernel module I'd like to build with any of make, make debug, make test, where the only difference between each one is a -D option to the compiler. This is essentially the same question as Creating a debug target in Linux 2.6 driver module makefile, but that one was marked as answered, and my question remains, after trying a few other things as well.
I've tried the deprecated EXTRA_CFLAGS option in my makefile:
debug:
$(MAKE) -C $(KDIR) M=$(PWD) EXTRA_CFLAGS="-DDEBUG" modules
as well as the newer ccflags-y option (doesn't seem to work even outside of the debug target):
ccflags-y := -DDEBUG
debug:
$(MAKE) -C $(KDIR) M=$(PWD) modules
and setting CFLAGS just before the debug target:
debug: CFLAGS_main.o=-DDEBUG
debug:
$(MAKE) -C $(KDIR) M=$(PWD) modules
but the only way I've found to accomplish what I want is with a separate build script:
#!/bin/sh
case "$1" in
debug)
make CFLAGS_main.o=-DDEBUG
;;
*)
make
;;
esac
Is there no way to do this directly in the makefile when building a kernel module??
You should be able to use your original version that used EXTRA_CFLAGS, but just replace EXTRA_CFLAGS with ccflags-y:
debug:
$(MAKE) -C $(KDIR) M=$(PWD) ccflags-y="-DDEBUG" modules
or replace it with CFLAGS_main.o to apply the CFLAGS to a single object:
debug:
$(MAKE) -C $(KDIR) M=$(PWD) CFLAGS_main.o="-DDEBUG" modules
EDIT
As mentioned by the OP Roger Dueck, setting variables on the make command line has a global effect. It overrides any setting of the same variables within the makefiles which may be undesirable, especially for a globally used variable such as ccflags-y. To avoid this, use your own makefile variable. In the "normal" part of the Makefile that invokes $(MAKE) on the "KBuild" part, change the debug: target to the following, using a custom variable of your choice (I used FOO_CFLAGS here):
debug:
$(MAKE) -C $(KDIR) M=$(PWD) FOO_CFLAGS="-DDEBUG" modules
In the "KBuild" part of the Makefile invoked by the above rule, use the following to append the custom CFLAGS from FOO_CFLAGS to ccflags-y:
ccflags-y += $(FOO_CFLAGS)
I'm writing a character driver to sit on top of a modified version of ahci in the source tree. I basically have something that looks like this:
topdir
|
|- Makfile
|
|- mod_ahci
| | - Makefile, codefiles
|
|- char_interface
| | - Makefile, codefiles
now, char_interface requires symbols from mod_ahci. I have the appropriate EXPORT_SYMBOL() macro use for the symbols I need to export. However, I'm having trouble getting the makefiles right to pick up the header file in mod_ahci from char_interface. My toplevel Makefile
ifneq ($(KERNELRELEASE),)
obj-y := mod_ahci/ char_interface/
else
KERNELDIR ?= /lib/modules/$(shell uname -r)/build
PWD := $(shell pwd)
default:
$(MAKE) -C $(KERNELDIR) M=$(PWD) modules
modules_install:
$(MAKE) -C $(KERNELDIR) M=$(PWD) modules_install
endif
The makefile for char_interface (because the other builds just fine)
ifneq ($(KERNELRELEASE),)
ccflags-y += -I../mod_ahci
obj-m := char_interface.o
else
KERNELDIR ?= /lib/modules/$(shell uname -r)/build
default:
$(MAKE) -C $(KERNELDIR) M=$(shell pwd) modules
modules_install:
$(MAKE) -C $(KERNELDIR) M=$(shell pwd) modules_install
endif
clean:
-sudo rmmod ahcip
-rm -f *.ko* *.mod.* *.o modules.order Modules.symvers
I have referenced various text files in the kernel documentation. For example, I'm referring to .../Documentation/kbuild/makefiles.txt right now as well as .../Documentation/kbuild/modules.txt. Whenever I build, I'm getting /home/captaink/devel/kmodtests/char_interface/char_interface.c:2:22: error: mod_ahci.h: No such file or directory. There is a file named mod_ahci.h in the directory ../mod_ahci. What am I getting wrong with my use of ccflags-y in the makefile for the char driver?
Thanks
After some digging, I found the answer to the problem. I was misunderstanding what was happening with the makefile's that I was viewing from LDD3 and the kernel documentation (which is, apparently, exactly where O'Reilly took their examples). The build system actually changes directories into /usr/src/kernels/$(uname -r)/build (or similar) because this is why my header file wasn't being found by the compiler.
I'm not saying this is an elegant way of doing this, but here's how I fixed it. The makefile in the top directory now looks like:
ifneq ($(KERNELRELEASE),)
obj-y := mod_ahci/ char_interface/
else
KERNELDIR ?= /lib/modules/$(shell uname -r)/build
PWD := $(shell pwd)
default:
$(MAKE) -C $(KERNELDIR) M=$(PWD) TOP_DIR=$(PWD) modules
modules_install:
$(MAKE) -C $(KERNELDIR) M=$(PWD) modules_install
endif
And the makefile in the subdirectory containing the char driver interface looks like:
ifneq ($(KERNELRELEASE),)
ccflags-y += -I$(TOP_DIR)/mod_ahci
obj-m := char_interface.o
else
KERNELDIR ?= /lib/modules/$(shell uname -r)/build
default:
$(MAKE) -C $(KERNELDIR) M=$(shell pwd) modules
modules_install:
$(MAKE) -C $(KERNELDIR) M=$(shell pwd) modules_install
endif
clean:
-sudo rmmod ahcip
-rm -f *.ko* *.mod.* *.o modules.order Modules.symvers
As you can tell, the makefiles have been copied extensively. The subdirectories probably don't need the "shared" makefile stuff in them because that's taken care of by the higher level makefile. Nevertheless, the modules now build and the character driver I have knows of the exported symbols I made in my modified ahci driver.
I hope this may help someone who's a neophyte, like myself, to the Linux kernel build world and Linux kernel drivers.
Eg: a common device module's Makefile
obj-m:=jc.o
default:
$(MAKE) -C /lib/modules/$(shell uname -r)/build M=$(shell pwd) modules
clean:
$(MAKE) -C /lib/modules/$(shell uname -r)/build M=$(shell pwd) modules clean
I consider if I can set CFLAGS to the file. When I change default section to
$(MAKE) -O2 -C /lib/modules/$(shell uname -r)/build M=$(shell pwd) modules
But it didn't work.
Any help? Thanks a lot.
-O2 would be an option to make (or $(MAKE), as you're using it) in what you tried. Obviously, the compiler (probably gcc) needs this flag, not make.
Kbuild understands a make variable named CFLAGS_modulename.o to add specific C flags when compiling this unit. In your case, your module object will be jc.o, so you can specify:
CFLAGS_jc.o := -O2
and it should work. Add V=1 to your $(MAKE) lines to get a verbose output and you should see -O2 when jc.c is being compiled.
You can find more about compiling modules in the official documentation.
You can also use
ccflags-y := -O2
This will be applied to all of the source files compiled for your module with the Makefile. This is indirectly documented in the link provided by eepp in Section 4.2
I am compiling one C file in Ubuntu but I am getting an error in including a header file. My Makefile is as follows:
obj-m := ov7725.o
CC = /opt/arm-linux-gnueabi/bin/arm-linux-gnueabi-gcc
EXTRA_CFLAGS +=-march=armv5
CFLAGS += -I /usr/local/arm/3.3.2/arm-linux/sys-include/linux
#LINUXKERNEL_INSTALL_DIR = /lib/modules/2.6.32-21-generic/build
#CFLAGS = -Wall -I $(LINUXKERNEL_INSTALL_DIR)
#export LINUXKERNEL_INSTALL_DIR CROSS_COMPILE CFLAGS PLATFORM
KDIR := /home/mayank/DM355SDK789311old/fs/fs/lib/modules/2.6.29-ridgerun-davinci1/build
#/lib/modules/2.6.32-32-generic-pae/build
PWD := $(shell pwd)
default:
# $(MAKE) -C $(KDIR) M=$(PWD) modules
make -C $(KDIR) ARCH=arm CROSS_COMPILE=/opt/arm-linux-gnueabi/bin/arm-linux- gnueabi- M=`pwd` modules
#all:
# $(CROSS_COMPILE) gpio_custom_dir_driver.c -o hello
clean:
rm -rf *o user_gpio
But even after including the line with CFLAGS in the makefile, I am getting an error for one header file not included which is present in the included directory.
Is there any other way, how can I include header files in a makefile?
Your CFLAGS and EXTRA_CFLAGS are not applied correctly. In makefile they are just common names for C compiler options/definitions and have to be added into command line invoking compiler (CROSS_COMPILE), but not through environment variables (as you tried to do with export - which is apparently wrong in makefile). You have to have something similar to the following in your makefile:
<target>:
$(CROSS_COMPILE) $(CFLAGS) $(EXTRA_CFLAGS) ....
I'm trying to cross compile a helloworld kernel (2.6.x) module for ARM architecture on my intel x86 host.
The codesourcery tool chain for ARM is located at: /home/ravi/workspace/hawk/arm-2009q3
The kernel source is located at :/home/ravi/workspace/hawk/linux-omapl1
My Makefile:
ARCH=arm
CROSS_COMPILE=arm-none-linux-gnueabi
obj-m := Hello.o
KDIR := /home/ravi/workspace/hawk/linux-omapl1
PWD := $(shell pwd)
default:
$(MAKE) -C $(KDIR) SUBDIRS=$(PWD) modules
clean:
$(MAKE) -C $(KDIR) SUBDIRS=$(PWD) clean
When i run make, the .ko produced is that of my host machine which means the makefile is invoking the native compiler instead of the cross compiler.What am I doing wrong? The cross compiler's binaries are in my path.
Putting ARCH and CROSS_COMPILE in the Makefile doesn't work. You need to put them on the command line:
make ARCH=arm CROSS_COMPILE=arm-none-linux-gnueabi-
Replace
ARCH=arm
CROSS_COMPILE=arm-none-linux-gnueabi
by
export ARCH:=arm
export CROSS_COMPILE:=arm-none-linux-gnueabi-
this will also work if you do not want to give these parameter command line each time.
Sidenote: SUBDIRS= is deprecated in favor of M=.
could you try, you forgot to add ARCH and CROSS_COMPILE into the default and clean
ARCH=arm
COMPILER=arm-none-linux-gnueabi
obj-m := Hello.o
KERNELDIR := /home/ravi/workspace/hawk/linux-omapl1
PWD := $(shell pwd)
default:
$(MAKE) -C $(KERNELDIR) M=$(PWD) ARCH=$(ARCH) CROSS_COMPILE=$(COMPILER) modules
clean:
$(MAKE) -C $(KERNELDIR) M=$(PWD) ARCH=$(ARCH) clean
adding export at the end of your Makefile variable declarations will make them available to subshells. and add the dash to the CROSS_COMPILE prefix as JayM pointed out, and M instead of SUBDIRS as user502515 answered.
and it's generally a good idea to use := rather than = in a Makefile, so the variable only gets interpolated once. really doesn't matter in this particular case though.
ARCH := arm
CROSS_COMPILE := arm-none-linux-gnueabi-
obj-m := Hello.o
KDIR := /home/ravi/workspace/hawk/linux-omapl1
PWD := $(shell pwd)
export
default:
$(MAKE) -C $(KDIR) M=$(PWD) modules
clean:
$(MAKE) -C $(KDIR) M=$(PWD) clean
MODULES := hola_kern.o
#guest architecture
ARCH := arm
CROSS_COMPILE := arm-linux-gnueabi-
obj-m := $(MODULES)
#path of the arm compiled kernel
ROOTDIR := /home/aldo/c/proyectos/prefixa/work/kernels/linux-omap-5f0a6e2
MAKEARCH := $(MAKE) ARCH=$(ARCH) CROSS_COMPILE=$(CROSS_COMPILE)
all: modules
modules:
$(MAKEARCH) -C $(ROOTDIR) M=${shell pwd} modules
clean:
$(MAKEARCH) -C $(ROOTDIR) M=${shell pwd} clean