I have to write a VHDL code that calculates the 10^x function for integer values of x between zero and nine (including zero and nine). Entity should have one 4-bit unsigned integer (std_logic_vector) type input and one 32-bit unsigned integer (std_logic_vector) type output. 32 bit width is enough for 10^9. I have to use the LUT (Look-up table) logic for the solution. For this, I should use the signal assignment and with-select structure in the architecture block without using the process at all. By using with-select, I will have determined with a fixed assignment what the output (LUT) will be for each value of x.
Error when i start synthesizing:
width mismatch in assignment; target has 32 bits, source has 1 bits
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity main is
Port (
input : in std_logic_vector(3 downto 0);
output: out std_logic_vector(31 downto 0)
);
end main;
architecture Behavioral of main is
begin
with input select
output <= "00000000000000000000000000000001" when "0000", --10^0
"00000000000000000000000000001010" when "0001", --10^1
"00000000000000000000000001100100" when "0010", --10^2
"00000000000000000000001111101000" when "0011", --10^3
"00000000000000000010011100010000" when "0100", --10^4
"00000000000000011000011010100000" when "0101", --10^5
"00000000000011110100001001000000" when "0110", --10^6
"00000000100110001001011010000000" when "0111", --10^7
"00000101111101011110000100000000" when "1000", --10^8
"00111011100110101100101000000000" when "1001", --10^9
"0" when others;
end Behavioral;
You understood what the problem was, so this answer is just to show you how to avoid the external computation of your ten 32-bits constants (with VHDL 2008), thanks to the ieee.numeric_std_unsigned package and a constant array of 32-bits vectors, computed by a function:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std_unsigned.all;
entity main is
...
end main;
architecture Behavioral of main is
type w32_array is array(0 to 15) of std_ulogic_vector(31 downto 0);
function powers_of_ten return w32_array is
variable res: w32_array := (others => (others => '0'));
begin
for i in 0 to 9 loop
res(i) := to_stdulogicvector(10**i, 32);
end loop;
return res;
end function powers_of_ten;
constant pw10: w32_array := powers_of_ten;
begin
output <= pw10(to_integer(input));
end architecture Behavioral;
Note: and yes, it should be synthesisable, because it is the synthesizer that computes the constants during synthesis, not the synthesized hardware.
Related
I want to slice a std_logic_vector in VHDL obtaining parts of it of fixed dimensions.
The general problem is:
din N*M bits
dout M bits
sel clog2(N) bits
Expected behaviour in an example (pseudocode): input 16 bit, want to slice it in 4 subvectors of 4bit each.
signal in: std_logic_vector(N*M-1 downto 0);
signal sel: integer;
-- with sel = 0
output <= in(N-1:0);
--with sel = 1 output <= in(2N-1:N)
-- with sel = 2
output <= in(3N-1:2N)
.....
--with sel = M-1
output <= in(M*N-1:(M-1)N)
I know a couples of way to do this, but I don't know which one is the best practice and give the best results in synthesis.
the entity
din: in std_logic_vector(15 downto 0);
dout: out std_logic_vector(3 downto 0);
sel: in std_logic_vecotor(1 downto 0)
CASE STATEMENT
case sel is
when "00" => dout <= din(3:0);
when "01" => dout <= din(7:4);
when "10" => dout <= din(11:8);
when "11" => dout <= din(15:12);
when others => ....`
It clearly implement a mux, but it's not generic at all and If the input gets big it's really hard to write and to codecover.
INTEGER INDEXING
sel_int <= to_integer(unsigned(sel));
dout <= din(4*(sel_int+1) - 1 downto 4*sel_int);
Extremely easy to write and to mantain, BUT it can have problems when the input is not a power of 2. For example, if I want to slice a 24bit vector in chunks of 4, what happen when the integer conversion of sel brings to the index 7?
A STRANGE TRADEOFF
sel_int <= to_integer(unsigned(sel));
for i in 0 to 4 generate
din_slice(i) <= din(4*(i+1)-1 downto 4*i);
end generate dout <= din_slice(sel_int);
I'm searching a solution that is general enough to be used with various input/output relationships and safe enough to be synthesized consistently everytime.
The Case statement is the only one with the Others case (that feels really safe), the other solutions rely on the slv to integer conversion and indexing that feels really comfortable but not so reliable.
Which solution would you use?
practical usecase
I have a 250bit std_logic_vector and I need to select 10 contigous bits inside of it starting from a certain point from 0 to 239. How can I do that in a way that is good for synthesis?
There is another option that is accepted by tools that allow VHDL 2008 (which includes Vivado and Prime Pro). You can use an unconstrained 2d type from a package:
type slv_array_t is array(natural range <>) of std_logic_vector; --vhdl 2008 unconstrained array type
then you can simply select which port you want. And it is as generic as you like.
library ieee;
use ieee.std_logic_1164.all;
use work.my_pkg.all;
entity mux is
generic (
N : natural;
M : natural
);
port (
sel : in natural;
ip : in slv_array_t (N-1 downto 0)(M-1 downto 0);
op : out std_logic_vector (M-1 downto 0);
);
end entity;
architecture rtl of mux is
begin
op <= ip(sel);
end architecture;
First you must extend the incoming data to be sure to have always as much bits as you need for connecting all multiplexer inputs (see the code below, process p_extend).
This will not create any logic at synthesis.
Second you must convert the resulting vector into an array, which you can access later by an index (see the code below, process p_create_array).
Again this will not create any logic at synthesis.
At last you must access this array by the select input signal (see the code below, process p_mux).
library ieee;
use ieee.std_logic_1164.all;
entity mux is
generic (
g_data_width : natural := 250;
g_slice_width : natural := 10;
g_sel_width : natural := 5;
g_start_point : natural := 27
);
port (
d_i : in std_logic_vector(g_data_width-1 downto 0);
sel_i : in std_logic_vector(g_sel_width-1 downto 0);
d_o : out std_logic_vector(g_slice_width-1 downto 0)
);
end entity mux;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
architecture struct of mux is
signal data : std_logic_vector(g_slice_width * 2**g_sel_width-1 downto 0);
type t_std_logic_slice_array is array (natural range <>) of std_logic_vector(g_slice_width-1 downto 0);
signal mux_in : t_std_logic_slice_array (2**g_sel_width-1 downto 0);
begin
p_extend: process(d_i)
begin
for i in 0 to g_slice_width * 2**g_sel_width-1 loop
if i+g_start_point<g_data_width then
data(i) <= d_i(i+g_start_point);
else
data(i) <= '0';
end if;
end loop;
end process;
p_create_array: process (data)
begin
for i in 0 to 2**g_sel_width-1 loop
mux_in(i) <= data((i+1)*g_slice_width-1 downto i*g_slice_width);
end loop;
end process;
p_mux: d_o <= mux_in(to_integer(unsigned(sel_i)));
end architecture;
How can I calculate the module of a vector?
As a vector is not a pre-defined type in VHDL it makes sense to me that there is no function implementing the modue of a vector. If there is such I have not found it.
This is basically a problem of obtaining the square root of a number, as the module can be defined as:
sqrt(a^2+b^2+...+n^2)
Implementing the sum of all the members of the vector squared is not a challenge so I think the most necessary part is having a function to calculate the square root of a number.
As far as I'm concerned there isn't any official package implementing this function. How to implement a function to calculate the module of a vector?
Or if you prefer it, how to implement a square root?
This is one possible solution. I will provide you 3 codes.
-The first one provides the type definition used for the vector. Its not important but it is needed to make it work.
-The second one is the package in which the function is defined. It is commented so that you can easily adapt it to any kind of vector. It can probably be upgraded to make it adapt by itself using some parameters by this works fine.
-The third one is a testbench to try it out.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package tipos is
constant bandas : positive := 4;
type vector32 is array (0 to bandas-1) of signed (31 downto 0);
end package tipos;
Be aware of calling properly the library with the vector definition. In my case it was compiled to work for the ModelSim simulation
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library work; use work.tipos.all;
package propios is
--function declaration.
function module (a : vector32; bands: natural) return unsigned;
end propios; --end of package.
package body propios is --start of package body
--definition of function
--based on: https://en.m.wikipedia.org/wiki/Methods_of_computing_square_roots#Binary_numeral_system_.28base_2.29
function module (a : vector32; bands: natural) return unsigned is --To adapt it to a diferent number of bits in the input vector:
--substitute the 71 for the needed number. Number of bits in each element of the vector *2 + power of two that can represent the maximum
--number of bands, or fields. In this case, 32bit numbers, maximum number of bands, 256, so 2^8. 32*2+8=72.
variable sum : unsigned(71 downto 0):= (others => '0');
variable b : unsigned(71 downto 0):=(0=>'0', 70 => '1', others => '0');
variable a_unsig: unsigned(31 downto 0):=(others =>'0');--for this vector use the same length as the input vector, 32bit in my case.
variable result: unsigned (71 downto 0):= (others => '0');
begin
for i in 0 to bands-1 loop--Sum of all the elements squared
a_unsig:=unsigned(a(i));
sum:=sum + (a_unsig * a_unsig);
end loop;
--Square root of sum
while b>sum loop--Do any needed changes here. You only have to change the 71's
b:='0'&'0'& b(71 downto 2);
end loop;
while (b/=0) loop
if (sum>=result+b) then
sum:=sum - (result + b);
result:=('0'& result(71 downto 1))+b;
else
result:='0'& result(71 downto 1);
end if;
b:='0' & '0' & b(71 downto 2);
end loop;
return result(35 downto 0);--sqrt(2^72)=2^36. Use half of the bits you put in place of 71
end module;
end propios; --end of the package body
And here is the testbench. Again take care of calling the packages properly
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.propios.all;
use work.tipos.all;
ENTITY test IS
END test;
Architecture simple of test is
signal a:vector32;
signal c: unsigned(35 downto 0);
signal b: natural:= 4;
begin
a(0)<="00000000110010011010011100000000";
a(1)<="00000000110010011010011100000000";
a(2)<="00000000110010011010011100000000";
a(3)<="00000000110010011010011100000000";
process
begin
wait for 200ps;
c<= module (a , b);
wait;
end process;
end simple;
I'm trying to use a function created by myself (it's the first time I try it so I might probably have done something wrong there).
When I try to compile I get the following error message: Error (13815): VHDL Qualified Expression error at Averageador.vhd(38): divide type specified in Qualified Expression must match unsigned type that is implied for expression by context
Divide is the name of my function. This function divides any 16bit unsigned value by an unknown unsigned value and gives the result as a fixed point 32bit unsigned value, where 16bit are on each side of the point. This is the code:
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
package propios is
--function declaration.
function divide (a : UNSIGNED; b: UNSIGNED) return UNSIGNED;
end propios; --end of package.
package body propios is --start of package body
--definition of function
function divide (a : UNSIGNED; b: UNSIGNED) return UNSIGNED is
variable a_int : unsigned(a'length+7 downto 0):= (others => '0');
variable b_int : unsigned(b'length-1 downto 0):=b;
variable r : unsigned(b'length downto 0):= (others => '0');
variable q : unsigned(31 downto 0):= (others => '0');
begin
a_int(a'length+7 downto 16):=a;
for i in a'length+7 downto 0 loop
r(b'length downto 1):=r(b'length-1 downto 0);
r(0) := a_int(i);
if (r>=q) then
r:=r-b_int;
q(i):='1';
end if;
end loop;
return q;
end divide;
--end function
end propios; --end of the package body
I return q which is a 32-bit unsigned.
This is a code in which I use the function and prompts the error message:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.propios.all;
ENTITY test IS --Con alimentación de datos posición a posición, no vector de golpe.
END test;
Architecture simple of test is
signal a:unsigned(15 downto 0);
signal b:unsigned(13 downto 0);
signal c: unsigned(31 downto 0);
begin
process
begin
a<="1100100110100111";
b<="00000000000010";
c<= divide(a,b);
end process;
end simple;
Any suggestions? Thank you
The problem is caused (as user1155120 said) by using the package std_logic_arith on the package and numeric_std on the test. Therefore, even if both are called unsigned they are not compatible with each other.
Both codes contained other errors which have also been corrected but were not related to this first error.
This is the package with a function for dividing 2 unsigned numbers with 16bits after the coma:
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
package propios is
--function declaration.
function divide (a : UNSIGNED; b: UNSIGNED) return UNSIGNED;
end propios; --end of package.
package body propios is --start of package body
--definition of function
function divide (a : UNSIGNED; b: UNSIGNED) return UNSIGNED is
variable a_int : unsigned(a'length+15 downto 0):= (others => '0');--Length is 16 bit longer than a
variable b_int : unsigned(b'length-1 downto 0):=b;
variable r : unsigned(b'length downto 0):= (others => '0');
variable q : unsigned(a'length+15 downto 0):= (others => '0');--Same length as a_int
variable i: natural;
begin
a_int(a'length+15 downto 16):=a;--the MSBits are "a" and the rest will be 0's
for i in a'length+15 downto 0 loop--division using a modified version of integer division (unsigned) with remainder as seen in:
--https://en.wikipedia.org/wiki/Division_algorithm
r(b'length downto 1):=r(b'length-1 downto 0);
r(0) := a_int(i);
if (r>=b_int) then
r:=r-b_int;
q(i):='1';
end if;
end loop;
return q;
end divide;
--end function
end propios; --end of the package body
This is a simple test to check its functionality:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.propios.all;
ENTITY test IS --Con alimentación de datos posición a posición, no vector de golpe.
END test;
Architecture simple of test is
signal a:unsigned(23 downto 0);
signal b:unsigned(13 downto 0);
signal c: unsigned(39 downto 0);
begin
process
begin
a<="000000001100100110100111";
b<="00000000010010";
wait for 200ps;
c<= divide (a , b);
wait;
end process;
end simple;
To check the result have in mind that the last 16 bits of the result are behind the fixed point.
I'm trying to use RAM in order to read/write. My address is an integer value and it should be a memory of integers. This is my code below but i keep getting an error.
This is from my data path where the address selection is from a register of integers.
Code:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity Mem is
generic( width: integer:=4;
depth: integer:=4;
addr: integer:=2);
port( Clock: in std_logic;
Enable: in std_logic;
Read: in std_logic;
Write: in std_logic;
Read_Addr: in integer;
Write_Addr: in integer;
Data_in: in integer;
Data_out: out integer
);
end Mem;
--------------------------------------------------------------
architecture behav of Mem is
type ram_type is array (0 to 31) of
integer;
signal tmp_ram: ram_type;
begin
-- Read Functional Section
process(Clock, Read)
begin
if (Clock'event and Clock='1') then
if Enable='1' then
if Read='1' then
-- buildin function conv_integer change the type
-- from std_logic_vector to integer
Data_out <= tmp_ram(conv_integer(Read_Addr));
else
Data_out <= (Data_out'range => 'Z');
end if;
end if;
end if;
end process;
-- Write Functional Section
process(Clock, Write)
begin
if (Clock'event and Clock='1') then
if Enable='1' then
if Write='1' then
tmp_ram(conv_integer(Write_Addr)) <= Data_in;
end if;
end if;
end if;
end process;
end behav;
----------------------------------------------------------------
Error:
Error (10514): VHDL aggregate error at Mem.vhd(41): can't determine type of aggregate -- found 0 possible types
Your faulty code is:
if Read='1' then
-- buildin function conv_integer change the type
-- from std_logic_vector to integer
Data_out <= tmp_ram(conv_integer(Read_Addr));
else
Data_out <= (Data_out'range => 'Z'); -- Faulty line
end if;
Data_out is an integer, not a std_logic_vector or derived type. Thus, it doesn't have a range (only arrays do, std_logic_vector beeing defined as an array of std_logic). Furthermore, it can't take the value of 'Z' since it is not an std_logic; integers can only be assigned integer values.
If you need Data_out to become high-impedance when enable is '1' and read is '0' as you described, you will need your memory output to use std_logic_vector or signed/unsigned.
Also, I should advise you against using integers without range if your target is synthesis. By VHDL standard, integers are 32 bits. Synthesis tool may optimized the netlist and use less bits, but you shouldn't count on it. Either constrain the range of your integers (signal x: integer range -4 to 3) or use signed/unsigned.
I have an input signal from ADC convertor that is 8 bits (std_logic_vector(7 downto 0)). I have to convert them to a 16 bits signal (std_logic_vector(15 downto 0)) for 16 bits signal processing to the 16 bits system.
If the 8 bit value is interpreted as signed (2's complement), then the general and standard VHDL conversion method is to use the IEEE numeric_std library:
library ieee;
use ieee.numeric_std.all;
architecture sim of tb is
signal slv_8 : std_logic_vector( 8 - 1 downto 0);
signal slv_16 : std_logic_vector(16 - 1 downto 0);
begin
slv_16 <= std_logic_vector(resize(signed(slv_8), slv_16'length));
end architecture;
So first the std_logic_vector is converted to a signed value, then the resize is applied, which will sign extend the signed value, and the result is finally converted back to std_logic_vector.
The conversion is rather lengthy, but has the advantage that it is general and works even if the target length is changed later on.
The attribute 'length simply returns the length of the slv_16 std_logic_vector, thus 16.
For unsigned representation instead of signed, it can be done using unsigned instead of signed, thus with this code:
slv_16 <= std_logic_vector(resize(unsigned(slv_8), slv_16'length));
architecture RTL of test is
signal s8: std_logic_vector(7 downto 0);
signal s16: std_logic_vector(15 downto 0);
begin
s16 <= X"00" & s8;
end;
This handles the conversion without having to edit the widths of the zeroes if either std_logic_vector changes:
architecture RTL of test is
signal s8: std_logic_vector(7 downto 0);
signal s16: std_logic_vector(15 downto 0) := (others => '0');
begin
s16(s8'range) <= s8;
end;
For completeness, yet another way which is occasionally useful:
-- Clear all the slv_16 bits first and then copy in the bits you need.
process (slv_8)
begin
slv_16 <= (others => '0');
slv_16(7 downto 0) <= slv_8;
end process;
I've not had to do this for vectors that I can recall, but I have had need of this under more complex circumstances: copying just a few relevant signals into a bigger, more complex, record was one time.
With the newly released VHDL-2019 standard you can do
larger_vec <= extend(shorter_vec);
where extend is a function defined as follows
function extend(vec : std_logic_vector) return target_vec of std_logic_vector is
variable result : std_logic_vector(target_vec'length - 1 downto 0) := (others => '0');
begin
assert vec'length <= target_vec'length report "Cannot extend to shorter vector";
result(vec'length - 1 downto 0) := vec;
return result;
end function;
Tool support is still a bit limited but at least one simulator supports this (Riviera-PRO).