I was just wondering, how could I concatenate two 8 bit vectors together into a 16-bit vector with odata_H having the MSB and odata_L having the LSB? Any help would be appreciated. The vectors are data points given off from an ADT7420 temperature sensor.
signal BCD: std_logic_vector(11 downto 0);
signal Bin_Temp: std_logic_vector(7 downto 0);
signal Bin_Acc: std_logic_vector(7 downto 0);
signal Buff_Temp: std_logic_vector(7 downto 0);
signal Buff_Acc: std_logic_vector(7 downto 0);
signal odata_L: std_logic_vector(7 downto 0);
signal odata_H: std_logic_vector(7 downto 0);
signal notEN: std_logic;
signal odataT: std_logic_vector(15 downto 0);
begin
odataT <= odata_H & odata_L;
Bin_Temp <= odataT(8 downto 1);
notEN <= not(EN);
I don't know why in this case the concatenation apparently doesn't work. Nevertheless, another way of achieving it is by using the resize() function of the numeric_std library.
library ieee;
use ieee.numeric_std.all;
[...]
odataT <= std_logic_vector(resize(signed(odata_H), odata_L'length));
The concatenation (odata_H, odata_L) will be resized with a length of length (16 in this case).
Of course unsigned instead of signed is possible, if applicable.
Related
I am making a 32 bit register with port and generic mapping. For some reason it says that the target signal Qt has 31 bits, while the input has 32 bits. Makes no sense right now. I looked through everything, and could not find how the Qt could be anything else than 32 bits since I declared the signal as signal Qt: std_logic_vector(31 downto 0);Any help is appreciated thanks.
I isolated the error line Qt <= D; and it still threw an exception. Down below is my minimally reproducible example.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.math_real.log2;
use ieee.math_real.ceil;
entity my_rege is
generic (N: INTEGER:= 32);
port ( clock, resetn: in std_logic;
E, sclr: in std_logic; -- sclr: Synchronous clear
D: in std_logic_vector (N-1 downto 0);
Q: out std_logic_vector (N-1 downto 0));
end my_rege;
architecture Behavioral of my_rege is
signal Qt: std_logic_vector (31 downto 0);
begin
Qt <= D;
Q <= Qt;
end Behavioral;
Did not realize that I had N: INTEGER:= 31 in the top file. When I changed the definition to N: INTEGER:= 32 the error disappeared. Sloppy coding on my part. I don't know why the tcl referenced this in the register file and not the top(lapfn) file. Is this because VHDL is written top down after port mapping, and it assumed the component from the top was the true bit-size?
entity LAPfn is
Port (resetn, clock, sclr, lap_db: in std_logic;
lap_select: in std_logic_vector (2 downto 0);
Data_in: in std_logic_vector (31 downto 0);
Lap_bits: out std_logic_vector (31 downto 0);
zlap: out std_logic;
cout: out std_logic_vector(2 downto 0));
end LAPfn;
architecture Behavioral of LAPfn is
component my_rege
generic (N: INTEGER:= 31);
port ( clock, resetn: in std_logic;
E, sclr: in std_logic; -- sclr: Synchronous clear
D: in std_logic_vector (N-1 downto 0);
Q: out std_logic_vector (N-1 downto 0));
end component;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.math_real.log2;
use ieee.math_real.ceil;
entity my_rege is
generic (N: INTEGER:= 32);
port ( clock, resetn: in std_logic;
E, sclr: in std_logic; -- sclr: Synchronous clear
D: in std_logic_vector (N-1 downto 0);
Q: out std_logic_vector (N-1 downto 0));
end my_rege;
architecture Behavioral of my_rege is
signal Qt: std_logic_vector (31 downto 0);
begin
Qt <= D;
Q <= Qt;
end Behavioral;
I have to project a specialized calculator on a Basys3 board using VHDL. The calculator should be able to group numbers using brackets, perform additions and substractions, AND and OR operations. For example, an expression could be: 4 + 5 AND 6 +(7 OR 1) - (4 AND 10)
The input numbers are 4 bit numbers (in my code I used 5 bit numbers, the most significant bit being the sign bit) and the output can be max. 16 bits long (i used 17 bits in my code, the most significant being the sign bit).
I wrote the code for the ALU (the adder/substractor, AND/OR) and I managed to make the calculator work for 2 numbers as inputs(using 2 in ports). This is the "main" code for the calculator, that i have written:
library IEEE;
use ieee.STD_LOGIC_1164.all;
use ieee.STD_LOGIC_UNSIGNED.all;
entity calculator is
port(X: in STD_LOGIC_VECTOR(4 downto 0); -- X(4) sign
Y: in STD_LOGIC_VECTOR(4 downto 0);
OPERATIE: in STD_LOGIC_VECTOR(4 downto 0);
CLK, CLR: in STD_LOGIC;
a_to_g: out STD_LOGIC_VECTOR(6 downto 0);
an: out STD_LOGIC_VECTOR(3 downto 0);
negativ: out std_logic);
end calculator;
architecture calculator of calculator is
component ALU is
port(A,B: in STD_LOGIC_VECTOR(16 downto 0);
COMANDA: in STD_LOGIC_VECTOR(4 downto 0);
RESULT: out STD_LOGIC_VECTOR(16 downto 0));
end component;
component BCD_7seg is
port(X: in STD_LOGIC_VECTOR(15 downto 0);
CLK, CLR: in STD_LOGIC;
a_to_g: out STD_LOGIC_VECTOR(6 downto 0);
an: out STD_LOGIC_VECTOR(3 downto 0));
end component;
signal OPERAND_1: STD_LOGIC_VECTOR(16 downto 0) := (others => '0');
signal OPERAND_2: STD_LOGIC_VECTOR(16 downto 0) := (others => '0');
signal TEMP_RESULT: STD_LOGIC_VECTOR(16 downto 0) := (others => '0');
begin
operand_1(3 downto 0) <= x(3 downto 0);
operand_1(16) <= x(4);
operand_2(3 downto 0) <= y(3 downto 0);
operand_2(16) <= y(4);
calculate: ALU port map(operand_1, operand_2, operatie, temp_result);
afis: BCD_7seg port map(temp_result(15 downto 0), clk, clr, a_to_g, an);
negativ <= temp_result(16);
end calculator;
However, the calculator should work for N numbers as inputs (using only one in port) and I don't know how to do it. I thought about memorising the whole expression(operartors and operands) in a FIFO or LIFO memory (but I'm not sure if that could work) and then making the calculations but I don't know how to calculate everything in the correct order given by the priorities and where(and how) to memorise the temporary results.
I thought that maybe you could give me some ideas, I'm new to VHDL, I'm a student and I have just started learning it and got stuck at this part in the project.
Thanks!
"Unsigned 8-bit Error Tolerant Adder" to add two 8-bit numbers in "vhdl code". I have already tried the code below.It gives these errors
** Error: C:/Modeltech_pe_edu_10.4a/examples/etl1.vhd(34): near "Signal": syntax error
** Error: C:/Modeltech_pe_edu_10.4a/examples/etl1.vhd(41): near "EOF": syntax error
#
code below
enter code here
library ieee;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use ieee.std_logic_unsigned.all;
entity adr is
port (a,b: in std_logic_vector(7 downto 0);
output : out std_logic_vector(7 downto 0));
end adr ;
architecture eta of adr is
signal hn,ln: std_logic_vector(7 downto 0);
signal parta2,partb2,hno:std_logic_vector(3 downto 0);
signal parta1,partb1: std_logic_vector(3 downto 0);
signal lno:std_logic_vector(3 downto 0);
begin
process (a,b)
begin
parta1<= a(7 downto 4); -- parta1<= a(7 downto 4);
parta2<= a(3 downto 0); --parta2<= a(3 downto 0);
partb1<= b(7 downto 4); --partb1<= b(7 downto 4);
partb2<= b(3 downto 0); -- partb2<= b(3 downto 0);
hno<= std_logic_vector(unsigned(parta1)+ unsigned(partb1)); --4 bit msb
lno<= std_logic_vector((unsigned(partb2))xor(unsigned(partb2)));--4bit lsb
Signal hn: std_logic_vector(7 downto 0) := hno(3 downto 0) & B"0000";-- concatenation of hn with zeros
Signal ln: std_logic_vector(7 downto 0) := B"0000" & lno(3 downto 0);--concatenation ln with zeros
output<=(hn or ln);
end process ;
.Thanks in Advance..
OK, you have three issues preventing this from compiling:
Signal hn: std_logic_vector(7 downto 0) := hno(3 downto 0) & B"0000";
In this line, you have already declared hn, and are trying to declare it again here. You can only declare a signal in the declarative region where most of your signals are defined. The second error is the B"0000"; I suspect you are trying to specify that your literal "0000" is binary, but this is the default when assigning to an std_logic_vector anyway. Your correct line would be:
hn <= hno(3 downto 0) & "0000";
The same errors are present in the line below this one.
The third error is pretty trivial. You have remembered an end process;, but forgotten the end architecture;.
How do I split 16-bit data into 2 8-bit data?
signal part : std_logic_vector (16 downto 0);
signal part_1 : std_logic_vector (8 downto 0);
signal part_2 : std_logic_vector (8 downto 0);
The part is actually 17 bit, since 16 downto 0 is a 17 bit range, and the part_* are likewise 9 bit.
If the ranges are 15 downto 0 and 7 downto 0, then you can do the split with:
part_1 <= part( 7 downto 0);
part_2 <= part(15 downto 8);
Btw, quote by Martin Fowler / Phil Karlton:
There are two hard things in computer science:
cache invalidation, naming things, and off-by-one errors.
Why are your signals 17 bits and 9 bits long? I think they should be 16 and 8...
signal part : std_logic_vector (15 downto 0);
signal part_1 : std_logic_vector (7 downto 0);
signal part_2 : std_logic_vector (7 downto 0);
begin -- architecture begin
part_1 <= part(15 downto 8);
part_2 <= part(7 downto 0);
Pretty simple stuff... I'm surprised you didn't run across this in looking at a VHDL example.
There's also aggregate target assignment:
library ieee;
use ieee.std_logic_1164.all;
entity foo is
end entity;
architecture fum of foo is
type fie is array (natural range 0 to 1) of std_logic_vector (7 downto 0);
signal part: std_logic_vector (15 downto 0);
signal part_1: std_logic_vector (7 downto 0);
signal part_2: std_logic_vector (7 downto 0);
begin
(part_1, part_2) <= fie'(part(15 downto 8), part(7 downto 0));
end architecture;
Which is admittedly more useful for extracting elements of records in one fell swoop. What's slick here is that there's no place there's any named signal of type fie.
The reason for the aggregate on the right hand side is because the element size has to match on both sides of the assignment operator, both aggregates are treated as if they are type fie.
Doing this with records allows you to extract elements of varying sizes. Extracting fields from CPU machine instruction formats comes to mind. It allows you to use simple names without requiring aliases for element selected names. (There would be no named record).
When the element size is the same on both sides you can simply use a target aggregate:
library ieee;
use ieee.std_logic_1164.all;
entity fie is
end entity;
architecture fum of fie is
signal part: std_logic_vector (2 downto 0);
signal part_1: std_logic;
signal part_2: std_logic;
signal part_3: std_logic;
begin
(part_1, part_2, part_3) <= part;
end architecture;
These aggregates all use positional association. You can also use named association. Record aggregates require an others choice represent at least one element and all the elements have to have the same type (e.g. std_logic_vector).
Just for completeness: you can also use aliases which makes the signal assignment obsolete:
signal part : std_logic_vector (15 downto 0);
alias part_1 : std_logic_vector(7 downto 0) is part(15 downto 8);
alias part_2 : std_logic_vector(7 downto 0) is part(7 downto 0);
Am having an output of 16 bit std_logic_vector from one block.But in the later stage i have to use only lower 8 bit std_logic_vector.it creating synthesis problem...please tell me how to avoid this..
If you have a 16-bit std_logic_vector you can access the individual bytes like this:
signal largeVariable : std_logic_vector(15 downto 0);
signal lower8bitsVariable : std_logic_vector(7 downto 0);
signal upper8bitsVariable : std_logic_vector(7 downto 0);
(...)
lower8bitsVariable <= largeVariable(7 downto 0); --Store the lower 8 bits of largeVariable
upper8bitsVariable <= largeVariable(15 downto 8); --Store the upper 8 bits of largeVariable