The technical note provided by Infrasolid provides some details. https://www.infrasolid.com/data/doc/Products/HISpower/HISpower-series-technical-note-operating-mode.pdf?c=20211109191000
Related
I'm doing network simulation using Omnet ++ software and castalia. so i want to know how to plot power consumption, RSSI value curves
thanks in advance
This question's answer is dependent on what software you're using exactly. OMNeT++ provides a suite and toolchain for visualization, but as user Thanassis points out below, Catalia has its' own specialized evaluation tools.
For general OMNeT++ simulations
The OMNeT++ tutorial covers this in quite a lot of detail. Basically:
tell OMNeT++ what data you're recording (by editing the .ned files) using the #statistic annotation
modify the simulation to track the data you're interested in, either over simulation time (referred to as vectors) or per simulation (referred to as scalars), basically using emit().
make sure that your simulation (omnetpp.ini) is set up to collect the statistics (by setting e.g. histogram or vector as the type of collected data)
use either the graphical OMNeT++ interface or your own scripts to analyze the output of the simulation (which is, by default, stored in a folder called results wherever you're running the simulation, unless you change that in the omnetpp.ini)
Please also refer to these related questions:
How to collect traffic data and macroscopic statistics in Veins?
Calculating end-to-end delay for SimpleServerApp in Veins-LTE
I have an small presentation about FPGA techonology. My questions is: If your FPGA has 85k logic cells, does this mean it can run 85k operations simultaneously?
What I am trying to achieve is to shock the audience with some crazy illustrated facts about FPGA technology or facts. The people who listens now very little about FPGA, so I want to impress them.
What's inside a 'cell' can vary per manufacturer, but the Xilinx definition (using this manufacturer as an example, as these are the devices that I'm familiar with) is one four-input look-up table, and one register. Xilinx devices are made up of a number of 'slices', and these contain a number of functional elements. These might include:
Look-up tables
Registers
Multiplexers
Logic for use in carry chains
etc
As an example, a Spartan6 LX4 has 600 slices, and the marketing material claims that this is equivalent to 3840 'logic cells'. You can look in the user guide for a device to determine exactly what is contained inside a slice.
In addition to this, there are other resources such as multipliers, memories, PLLs, etc.
I suppose you could say that one logic cell can perform one operation, but a single cell is only capable of very simple operations, for example an AND gate, 2:1 multiplexer, etc.
I would say no, but it depends on what you mean by an operation. A logic cell has the capability to implement a number of logical functions (and/or/xor), and it has the ability to hold a state with storage elements. These two functions are how every digital system under the sun operates. Even addition and subtraction are higher level constructs built on top of logical functions. As in other answers, FPGA manufacturers publish guides on what is inside of their logic cell. It is this fundamental cell that is stamped repeatedly in the die to create this "array" as in Field Programmable Gate "Array".
This yields a distinctly "more or less" answer. The logic blocks can be used in multiple modes, and you might even be able to pack more than one function in one (including with two independent outputs), but you must also be able to transport meaningful data to work on. It sounds like you have a 7z020 as an example. You may want to note that besides those logic cells, it also has 220 hardware multiply+add blocks. That amount is not random; the surrounding logic is enough to keep them fed in particular cases, every cycle. Looking in 7 Series FPGAs Configurable Logic Block User Guide (UG474), we find that the Logic Cells number given is an estimate of equivalent 4LUT+FF configurations. The reason this number is lower than the number of flipflops (106k) is that the input arguments for the two 5luts you can split a 6lut into must overlap.
i have to build a project that uses an FPGA with the software Modelsim. the project is a range finder or measuring tape.
I already know the basics of modelsim, but I've never done anything like this. the sensor that i am using is an Infra red proximity sensor. https://www.sparkfun.com/products/242 . I am aware that i will need to use an Analog to digital converter, in order for the fpga to recognize the sensor. this sensor also has to rely on is output voltage to determine the distance. the distance will then be displayed on an LCD screen. The problem i have is that i'm not sure where to start.
so if anyone can give any advice, a sample code for this problem or anything it would be appreciated.
Each of these subjects can be a large subject of their own. As it is, you should narrow down your question into something more specific -- where are you stuck? That said, here are some thoughts to help you narrow your questions.
You have correctly identified what you need to do: utilize an A/D converter, and display range (distance) on an LCD screen.
Let's break what you need to do in a little more details.
You need to interface with the A/D converter. For example, what pins are the data pins attached to on your FPGA? How do you need to clock the A/D? Basically, you need to figure out how to get digital samples into your FPGA logic.
You need to convert your digital samples from a voltage to a range. A lookup table is an excellent way to do this. The input to the lookup table will be (digital) voltage, the output will be range.
You need to learn how to interface with an LCD screen/panel. At minimum, you are going to have to learn how to draw/redraw a few characters on the screen representing the range.
Once you have these 3 components, you need to tie them together. The A/D interface in the FPGA will periodically generate voltage values, the lookup table will convert voltages to range, and then you will display the range value on your LCD.
Why do some NFC-modules have two transmitters? TX1 and TX2?
I really can't find what it's for... I was thinking about Single-end and differential signaling?
So there would be less noise?
Most NFC modules have two transmitter outputs pins. These are not two independent outputs but just the two pins of a single differential output.
The reason why a differential output is preferred by NFC modules is quite simple: It is often needed if the NFC chip only has a small supply voltage (3V is common). Since the output is capacitively coupled to the antenna, the antenna can be driven with twice the voltage compared to a single ended output.
That allows for twice the current, and hence twice the magnetic field in the antenna.
I'm trying to create two precise frequencies at the 100 MHz range which are just a few kHz apart. A PLL isn't is a solution since it can't multiply by such big values.
The only solution I came up with is XOR two frequencies to add them. However this creates other unwanted frequencies which can only be filtered with external components.
How can I do it?
The only method I can think of are to apply the techniques that are used to build "Time To Digital Converters", i.e., FPGA Based High Resolution Time to Digital Converter. This would allow you to create FPGA based oscillators at nearly any speed, at the cost of hardware resources.
If you plan to use this in a production environment, however, you have to deal with the influence of temperature and vdd on the resulting frequencies. I know that there are FPGA based, temperature compensated circuits for just this purpose, but I guess you'll have to dig rather deep into the matter.