Why do some NFC-modules have two transmitters? TX1 and TX2?
I really can't find what it's for... I was thinking about Single-end and differential signaling?
So there would be less noise?
Most NFC modules have two transmitter outputs pins. These are not two independent outputs but just the two pins of a single differential output.
The reason why a differential output is preferred by NFC modules is quite simple: It is often needed if the NFC chip only has a small supply voltage (3V is common). Since the output is capacitively coupled to the antenna, the antenna can be driven with twice the voltage compared to a single ended output.
That allows for twice the current, and hence twice the magnetic field in the antenna.
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1-1 What are the difference in delay times of the basic logic gates?
I found that NAND and NOR gates are preferred in digital circuit design for shorter delay time and that AND and OR gates might even be implemented with NOT and NAND/NOR gates.
1-2 Are there set or known difference in delay time between AND, OR, NOT gates?
For a typical fpga (LUT-based logical elements) there's no difference at all.
Single cell can implement a complex function based on its resulting truth table, and multiple expressions might be folded into single cell, so you wouldn't even find individual and/or/not "gates".
It might be different for ASIC, I don't know. But in a typical fpga you don't have gates, there are ram-based lookup tables, implementing complex functions of its inputs - 4-6 inputs, not just 2.
You'll find that in a big enough design the routing costs are much higher than delays in a single logical cell.
If you look at how these different gates are constructed you can see some of the reasons for differences. An inverter consists of one pull-up transistor and one pull down transistor. This is the simplest gate and is therefore potentially the fastest. A NAND has two pull-down devices in series and two pull-up transistors in parallel. The NOR is basically the opposite of the NAND. And yes: AND is usually just NAND + inverter.
The on resistance of a path will be higher with two transistors in series (making it slower), and the number of transistors connected to a single node will increase the captive load (making it slower). You can make things faster by using larger transistors (with lower on resistance) but that increases the load of whatever cell is driving it, which slows that cell down.
It is a big optimization problem which you probably shouldn't try to solve yourself. That is what the EDA tools are for.
Like most answers in life, it depends. There are many ways to build each type of logic gate and different types of transistors can be used to make each type of gate. You can build all gates from multiple universal gates like NAND and NOR. So the other gates would have a larger delay time. BJT transistors will have a larger delay than MOFET transistors. You can also use Schottky transistors to reduce delays compared to BJT. If you use an IC there are lots of components within the chip, some which may reduce delays and some that may increase delays. So you really have to compare what you are working with. Here is a video that shows the design of logic gates at the transistor level. https://youtu.be/nB6724G3b3E
I have an small presentation about FPGA techonology. My questions is: If your FPGA has 85k logic cells, does this mean it can run 85k operations simultaneously?
What I am trying to achieve is to shock the audience with some crazy illustrated facts about FPGA technology or facts. The people who listens now very little about FPGA, so I want to impress them.
What's inside a 'cell' can vary per manufacturer, but the Xilinx definition (using this manufacturer as an example, as these are the devices that I'm familiar with) is one four-input look-up table, and one register. Xilinx devices are made up of a number of 'slices', and these contain a number of functional elements. These might include:
Look-up tables
Registers
Multiplexers
Logic for use in carry chains
etc
As an example, a Spartan6 LX4 has 600 slices, and the marketing material claims that this is equivalent to 3840 'logic cells'. You can look in the user guide for a device to determine exactly what is contained inside a slice.
In addition to this, there are other resources such as multipliers, memories, PLLs, etc.
I suppose you could say that one logic cell can perform one operation, but a single cell is only capable of very simple operations, for example an AND gate, 2:1 multiplexer, etc.
I would say no, but it depends on what you mean by an operation. A logic cell has the capability to implement a number of logical functions (and/or/xor), and it has the ability to hold a state with storage elements. These two functions are how every digital system under the sun operates. Even addition and subtraction are higher level constructs built on top of logical functions. As in other answers, FPGA manufacturers publish guides on what is inside of their logic cell. It is this fundamental cell that is stamped repeatedly in the die to create this "array" as in Field Programmable Gate "Array".
This yields a distinctly "more or less" answer. The logic blocks can be used in multiple modes, and you might even be able to pack more than one function in one (including with two independent outputs), but you must also be able to transport meaningful data to work on. It sounds like you have a 7z020 as an example. You may want to note that besides those logic cells, it also has 220 hardware multiply+add blocks. That amount is not random; the surrounding logic is enough to keep them fed in particular cases, every cycle. Looking in 7 Series FPGAs Configurable Logic Block User Guide (UG474), we find that the Logic Cells number given is an estimate of equivalent 4LUT+FF configurations. The reason this number is lower than the number of flipflops (106k) is that the input arguments for the two 5luts you can split a 6lut into must overlap.
i have to build a project that uses an FPGA with the software Modelsim. the project is a range finder or measuring tape.
I already know the basics of modelsim, but I've never done anything like this. the sensor that i am using is an Infra red proximity sensor. https://www.sparkfun.com/products/242 . I am aware that i will need to use an Analog to digital converter, in order for the fpga to recognize the sensor. this sensor also has to rely on is output voltage to determine the distance. the distance will then be displayed on an LCD screen. The problem i have is that i'm not sure where to start.
so if anyone can give any advice, a sample code for this problem or anything it would be appreciated.
Each of these subjects can be a large subject of their own. As it is, you should narrow down your question into something more specific -- where are you stuck? That said, here are some thoughts to help you narrow your questions.
You have correctly identified what you need to do: utilize an A/D converter, and display range (distance) on an LCD screen.
Let's break what you need to do in a little more details.
You need to interface with the A/D converter. For example, what pins are the data pins attached to on your FPGA? How do you need to clock the A/D? Basically, you need to figure out how to get digital samples into your FPGA logic.
You need to convert your digital samples from a voltage to a range. A lookup table is an excellent way to do this. The input to the lookup table will be (digital) voltage, the output will be range.
You need to learn how to interface with an LCD screen/panel. At minimum, you are going to have to learn how to draw/redraw a few characters on the screen representing the range.
Once you have these 3 components, you need to tie them together. The A/D interface in the FPGA will periodically generate voltage values, the lookup table will convert voltages to range, and then you will display the range value on your LCD.
Partly a coding problem, partly math problem.
Q1. I have an iOS device with compass active. If it knows I'm moving through the field of an iBeacon - or the Beacon is moving through my detection range - would it be possible for a phone to work out (roughly) the relative direction/bearing of that beacon with a series of readings by comparing signal strengths? Has anyone had a try at this?
Q2. Would it be possible to change the Major and Minor values of a beacon regularly (eg: every second) to pass small pieces of info - such as a second user's Bearing and Course?
Q1. It MIGHT be possible but you would need a controlled environment. Either the beacon or the phone needs to be fixed. You also need to be in an area with no obstructions or sources of radio interference.
Then you'd need to use the signal strength (which is sloppy and varies by a fair amount) as one input, and the device's heading info (which is also grossly inaccurate) and do some petty gnarly math on it.
Assuming you could work out the math, the slop in the input readings might make the results too iffy to be useful. (For example, how would you distinguish moving directly towards the beacon from moving 30 degrees to one side or the other? The signal strength would still increase, just not as quickly.
And your algorithm would have to deal with edge cases like moving along a circle around the beacon. In that case the signal strength should not change.
My gut is that even with clever algorithms that input data is just too unreliable to make much sense out of it, beyond "getting warmer" and "getting colder."
As mentioned above, you'd have to track your device's movement within the field, including distance covered and direction, then with multiple readings of signal strength you could theoretically calculate relative direction to the beacon to some degree of accuracy.
As to your second question about changing the minor version number, I have not seen any beacon APIs that allow that, either from the beacon manufacturers or from Apple's implementation.
However, a typical beacon is an ARM or other low power processor with a BLE transceiver, running a program. In theory it should be possible to create your own iBeacon transmitter that changed one of the parameters in order to transmit changing information. You'd have to set up the iOS device with the beacon region only specifying the UUID or UUID and major ID (depending on whether you wanted to change just the minor or change both the major and minor ID in order to transmit changing information.)
Note, too, that iBeacons are a special case of BLE, and the BLE standard does support the sending of arbitrary, changing data. You might be better off implementing your own BLE scheme either instead of or in addition to iBeacons.
I'm trying to create two precise frequencies at the 100 MHz range which are just a few kHz apart. A PLL isn't is a solution since it can't multiply by such big values.
The only solution I came up with is XOR two frequencies to add them. However this creates other unwanted frequencies which can only be filtered with external components.
How can I do it?
The only method I can think of are to apply the techniques that are used to build "Time To Digital Converters", i.e., FPGA Based High Resolution Time to Digital Converter. This would allow you to create FPGA based oscillators at nearly any speed, at the cost of hardware resources.
If you plan to use this in a production environment, however, you have to deal with the influence of temperature and vdd on the resulting frequencies. I know that there are FPGA based, temperature compensated circuits for just this purpose, but I guess you'll have to dig rather deep into the matter.