how to chose over set_false_path, set_multicylce_path, set_max_skew - fpga

Question

This problem has been bothering me for a long time， based on my understanding:
set_false_path is a timing constraints which is not required to be optimized for timing. we can use it for two flop synchronizer since it is not required to get captured in a limited time.
set_clock_groups It saves us from defining too many false paths.
set_multicylce_path used to relax the path requirement when the default worst requirement is too restrictive. we can set the set/hold clk to fix the timing. we can use it in cross domain
set_max_skew/set_max_delay -datapath_only used on asynchronous FIFO style that does the whole convert read/write pointers from binary to gray. Looks like set_max_skew help with control the skew between the multiple bits of the gray code to the double-flop synchronizers. Why do you need the "datapath_only"? Just using set_multicycle_path will also pass the timing check.
So in summary, all those methods can be used in async fifo right?
And the set_false_path is the most simple way. No need to worry about the mcp cycle or max delay. I guess we use it only when the logic between 2 FF is "combinational"? Can we use it when there are sequence logic between 2 cross domain FF?
If ignoring all timing calculations using FP is bad, when is it a good time to use it? In theory I can replace all the FP with MCP.
What factors do you need to consider in order to choose the most suitable constraints?

Answer 1

So apparently there are 4 following questions in your post:
Question 1: So in summary, all those methods can be used in async fifo right?
Question 2: And the set_false_path is the most simple way. No need to worry about the mcp cycle or max delay. I guess we use it only when the logic between 2 FF is "combinational"? Can we use it when there are sequence logic between 2 cross domain FF?
Question 3: If ignoring all timing calculations using FP is bad, when is it a good time to use it? In theory I can replace all the FP with MCP.
Question 4: What factors do you need to consider in order to choose the most suitable constraints?
Following are the 4 answers to aforementioned questions:
Answer 1: As shown below in figure, with an asynchronous FIFO, data can arrive at arbitrary time intervals on the transmission side, and the receiving side pulls data out of the queue as it has the bandwidth to process it.
Therefore, Yes, you can use all those optimizations/constraints/methods for asynchronous FIFO.
Answer 2: Yes set_false_path can be considered as one of the most simplest. And as the following figure shows, you are right we use when the logic between 2 FF is "combinational"?
Furthermore, based on my understanding, we do not use for sequence logic.
Answer 3: A false path is similar to the multicycle path in that it is not required to propagate signals within a single clock period. The difference is that a false path is not logically possible as dictated by the design. In other words, even though the timing analysis tool sees a physical path from one point to the other through a series of logic gates, it is not logically possible for a signal to propagate between those two points during normal operation. The main difference between a multicycle path with many available cycles (large n) versus a false path is that the multicycle path will still be checked against setup and hold requirements and will still be included in the timing analysis. It is possible for a multicycle path to still
fail timing, but a false path will never have any associated timing violations.
Hence use a multicycle path in place of a false path constraint when:
your intent is only to relax the timing requirements on a synchronous path;
but
the path still must be timed, verified and optimized.
Answer 4:
Although a very valid question yet too broad. It all depends on the underlying design. Most implementation tools for FPGA layout have a plenty of optimization options. And obviously not all constraints are used by all steps
in the compilation flow. Based on my experience and citing from Reference 1 the constraints that must be included in every design include all clock definitions,
I/O delays, pin placements, and any relaxed constraints including multicycle
and false paths.
Following two main references can further explain you to understand the the use of constraints:
Reference 1
Reference 2