I tried on Latitude 3500 Ubuntu kernel 5.13.1. Its pci switch 1d:0.0 is rp supporting aer/dpc, and connected to Eth port at 1:0.0 that support aer.
With aer_inject I can run all examples, generate aer interrupt from Eth port. I modified dpc.c to enable rp dpc and monitored dpc irq/handler, no dpc irq can be raised. Then I added code on aer_inject to replace the irq_inject_interrupt() with dpc s/w trigger which works. My questions are:
1.Why there is no dpc_inject? any possibility to do a dpc_inject?
2.irq_inject_interrupt() works for aer because its status reg is r/w, not work for dpc because its status reg is RO?
3.Per spec certain aer errors shall raise dpc interrupt, it doesn't work. would the the reason be I used aer_inject no real h/w error happens?
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I'm trying to enable USB 2.0 Host on an AST2500 based board. I'm using the latest obmc-phosphor-image from GitHub which contains Linux 5.10.30. EHCI seems to start in QEMU but fails on real HW. I enabled ehci0 (or ehci1) in the device tree, added the necessary drivers to Linux and I get the following error message during boot-up:
ehci-platform 1e6a1000.usb: USB 2.0, controller refused to start: -110
I investigated EHCI registers a bit and found that when ehci_run() function in ehci-hcd.c would start EHCI (by setting CMD_RUN bit) it remains halted, HCHalted bit in USBSTS register remains 1.
I also saw that the frame index register starts to count when CMD_RUN is asserted. Clock and reset bits in SCU registers are set properly by pinctrl and clk drivers.
Contents of the periodic list buffer and the asynchronous QH buffer seem to be OK. But EHCI still doesn't start.
Strangely UHCI (USB 1.1 host) seems to work properly.
Did maybe somebody manage to get EHCI working on real AST2500 or similar hardware?
Thanks for any advice.
I'm testing a mcu PIC in ide ccs, in loopback mode. But when I send a message, can see it in can-bus.
The datasheet says:
The Loopback mode is a silent mode, meaning no messages will be transmitted while in this state (including error flags or Acknowledge signals). The TXCAN pin will be in a recessive state.
at read the register CANSTAT, I see in bit 7-5(OPMODE) - 010b, which means the operation mode is correct, but the loopback not silent.
where am I wrong in this?
I am working on the lowRISC recently, and I want to add Ethernet support for it. I have added the Ethernet IP and have wired it to both AXI bus and Ethernet PHY, and I added the Ethernet interrupt to the interrupt wire just like uart and spi do.
Now I am working to write a driver in linux kernel to support my Ethernet. But I don't find the handle functions to uart and spi interrupts, just 2 interrupts called IRQ_SOFTWARE and IRQ_TIMER(which in file arch/riscv/include/asm/irq.h).
How does the lowRISC chip handle the uart and spi interrupts? And What should I do to handle the interrupt of ethernet on lowRISC chip?
I'm going through the probe function of the following driver
/drivers/net/ethernet/smsc/smsc911x.c
Inside the probe function it has been commented that
/* Ensure interrupts are globally disabled before connecting ISR */
smsc911x_disable_irq_chip(dev);
retval = request_irq(dev->irq, smsc911x_irqhandler,
irq_flags | IRQF_SHARED, dev->name, dev);
But I don't see it is TRUE in case of every other device driver ,so why it is in case of this particular Network driver?
Why interrupts are globally disabled before connecting ISR?
The comment says that the interrupts are disabled globally; but as in the function call below, the interrupts are disabled only for the device smsc driver attaches to. This is normally done to avoid getting interrupts well before driver preparing itself for processing interrupts. Since this is for an Ethernet driver, interrupts are enabled most likely during interface up.
The code snip in question gets executed during module load which is well before the interface up.
I have written a custom PLB core for my design, and added interrupt functionality during custom core generation. Interrupt generation logic is designed in custom peripheral. For interrupt control, I added XPS interrupt controller (v2.01a) to the system and connected my custom core's interrupt ports to INTC via master bus. However, as I need to connect IRQ output of INTC to Interrupt input of Microblaze (v8.40), I cannot connect those two ports using Ports tab of System Assembly View, there is no connection option except external port and core's itself. I tried to do it manually on .MHS file, but still I cannot see IRQ and Interrupt ports connected in Graphical Design View. Besides, in Bus Interfaces tab of Assembly View, I can see INTERRUPT port of Microblaze but again, no change can be made.
Use AXI_INTC insteed of XPS_INTC and it should work.
There you will find two bus :
AXI BUS
INTERRUPT BUS.
You will be able to connect the interrupt bus to your MicroBlaze component