I am working on the lowRISC recently, and I want to add Ethernet support for it. I have added the Ethernet IP and have wired it to both AXI bus and Ethernet PHY, and I added the Ethernet interrupt to the interrupt wire just like uart and spi do.
Now I am working to write a driver in linux kernel to support my Ethernet. But I don't find the handle functions to uart and spi interrupts, just 2 interrupts called IRQ_SOFTWARE and IRQ_TIMER(which in file arch/riscv/include/asm/irq.h).
How does the lowRISC chip handle the uart and spi interrupts? And What should I do to handle the interrupt of ethernet on lowRISC chip?
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I have zynq with carrier board. This board has a ethernet port, but I need two ports. Can I create new ethernet port with fpga IO pins. Is it possible or do have any different idea about that?
My board is Picozed FMC Carrier.
Short: No!
An ethernet interface is a special type of analogue interface with lots and lots of special circuitry on it. You can NOT get the right behavior with a digital interface.
If your FPGA has a USB port you might try to add a USB <=> Ethernet converter chip to get a second Ethernet port. (like all the old Raspberry-Pi's have).
I have developed Xilinx Zynq SoC c program for transmitting customized raw ethernet packets for testing purpose.
When I connect the Zynq SoC board with a patch cable to the Desktop I get the following packet on Wireshark.
WireShark Packet Screen Capture
But when I bring a switch in between the two i.e. Zynq SoC connected to the switch and Desktop connected to the same switch the above packet sent from Zynq SoC isn't visible on Wireshark.
Can someone point me out what's wrong in the packet I am sending that makes the switch reject the packet I am sending.
I would like to mention that the zynq board doesn't transmit any packets except from the above.
Thanks
As per, rpi3 device tree, it has two spi buses i.e spi0 and spi1. spi0 bus supports 2 chip select [spi0.0, spi0.1] and spi1 bus supports 3 chip select[spi1.0, spi1.1, spi1.2] pins. All these can be configured in config.txt using dtoverlay.
Now my rpi3 uses spi0.1 for touchscreen interface. I dont want to use spi0.0 because it may cause bus contention. So i need to connect my other peripheral on spi1.x bus.
When i am querying rpi3 for spi buses using getSpiBusList(), the ouput is [SPI0.0, SPI0.1]
How do i get around this issue?
Note:- Using android things 0.7-devpreview
According Raspberry Pi I/O pinout there is only SPI0.0 and SPI0.1 SPI buses pins, so you can't use SPI1.? bus even if you configure it in config.txt.
I have written a custom PLB core for my design, and added interrupt functionality during custom core generation. Interrupt generation logic is designed in custom peripheral. For interrupt control, I added XPS interrupt controller (v2.01a) to the system and connected my custom core's interrupt ports to INTC via master bus. However, as I need to connect IRQ output of INTC to Interrupt input of Microblaze (v8.40), I cannot connect those two ports using Ports tab of System Assembly View, there is no connection option except external port and core's itself. I tried to do it manually on .MHS file, but still I cannot see IRQ and Interrupt ports connected in Graphical Design View. Besides, in Bus Interfaces tab of Assembly View, I can see INTERRUPT port of Microblaze but again, no change can be made.
Use AXI_INTC insteed of XPS_INTC and it should work.
There you will find two bus :
AXI BUS
INTERRUPT BUS.
You will be able to connect the interrupt bus to your MicroBlaze component
I am new to Linux Device driver and trying to understand Linux device driver model which says a device must registered with its respected bus, be it the platform bus or real spi/i2c bus.
I could see the following macro which registered the i2c client device to its i2c bus.
module_i2c_driver(lm73_driver);
But I am not sure how it happen for a spi client device for example a CPLD/FPGA device sits on the spi bus.
Is such registrations based on the type of device?(block device or char device)