I am trying to program pic16f73 microcontroller, but in configuration bit setting there are no options to select internal or external clock.
Can any one help me to find the solution.
The PIC16F73 don't have an internal oscillator:
The PIC16F7X can be operated in four different oscillator modes. The user can program two configuration bits (FOSC1 and FOSC0) to select one of these four modes:
LP Low Power Crystal
XT Crystal/Resonator
HS High Speed Crystal/Resonator
RC Resistor/Capacitor
This controller always needs an external pullup resistor (e.g. 10k) on the MCLR pin.
From the datasheet, it looks like an external clock is required for PIC16F7X.
If you have a look at the datasheet Oscillator Configurations on the Configuration bits section (Page 91) there are four modes:
LP Low Power Crystal
XT Crystal/Resonator
HS High-Speed Crystal/Resonator
RC Resistor/Capacitor
On figure 12-1 of the datasheet, there is how to configure CRYSTAL/CERAMIC
RESONATOR.
By table 12-2 of the datasheet, the HS mode is for crystal frequency >= 4MHz the XT mode is for <=4MHz and the LP is for <= 200 KHz.
So the configuration mode is dependent on the crystal resonator connected. For more details datasheet has them all.
Related
I'm trying to change pin voltage on 'Altera cyclone 4 FPGA' in Quartus? I have changed it in a pin planner and source voltage. But, unfortunately, the voltmeter always show '3 - 3.3 V'.
Am I missing something. Please, advise.
You can't change pin voltages from Quartus. The I/O voltage is equal to the voltage you supply at VCCIO (for that particular I/O bank).
The Quartus setting is to tell the design tools what voltage your hardware will be using so that timing and power consumption calculations will be correct.
As shown by this table in the device datasheet, the I/O Standard and VCCIO voltage level are linked, you cannot select an I/O standard at a different voltage without changing the I/O supply voltage your PCB provides to the FPGA VCCIO pins.
I have an Arduino Uno R3 (actually, distributed from Elegoo but has the same exact components) and I thought about burning the ATMega 8 chip on it with a bootloader, using the "Arduino as ISP" feature on the Arduino IDE.
I looked at the specs for the ATMega 8 chip, and I would like to just ask - everywhere I've looked online, it says the default CPU clock speed is 16MHz, which makes sense because of the crystal clock onboard running at 16MHz. However, I'm not sure the code I have already written is safe:
#define SPI_CLOCK (16000000/6) // Internal clock speed 16 MHz for Arduino UNO.
I think that this code will be fine considering the specs. The example told me to set SPI_CLOCK to a value of 1000000/6, which slow enough for an ATtiny85 (# 1 MHz), but since I want to use the full functionality of the crystal I have onboard and want a faster clock speed, is it safe to set SPI_CLOCK directly to 16000000/6?
Any help will be appreciated.
Thanks!
Anyways, AterLux answered my question:
Setting SPI clock speed on the programmer only affects how fast you can flash the device. It does not change how the flashed code works – AterLux
I want to use hdmi monitor with cyclone V GX board, but I don't get an acknowledgement from adv7513 on i2c bus.
I think there is a problem with the address that I am sending at the beginning of the i2c transaction (I get no acknowledgement of address) I couldn't find information on whether PD/AD is low or high. Also I am not sure if i should use 7 or 8 bit address, so I would like some explanation.
I used i2c controller that i found online:
https://www.digikey.com/eewiki/pages/viewpage.action?pageId=10125324
signaltap result
I assume you haven't read the ADV7513 Programming Guide
The ADV7513 uses four I2C register maps. The SDA/SCL programming
address for the Main Register Map is 0x72 or 0x7A, based on whether
PD/AD is pulled high (10KΩ resistor to power supply = 0x7A) or pulled
low (10KΩ resistor to GND = 0x72) when power is applied to the
supplies. The user should wait 200ms for the address to be decided,
after the power supplies are high, before attempting to communicate
with the ADV7513 using I2C
I2C addresses are 7-bit or 10-bit not 8-bit. In this case it is 7-bit.
See I2C Specification. So if PD/AD is high, 7-bit address is 0x7A. In binary your 7 bits will be: 1111010. The R/W bit is the last bit of the first I2C 'address' byte but the vhd code you posted doesn't need that as part of the address, that's done separately.
addr : IN STD_LOGIC_VECTOR(6 DOWNTO 0); --address of target slave
rw : IN STD_LOGIC; --'0' is write, '1' is read
If you are still having problems, check your pull-ups, I2C SCL clock rate, ensure the master allows clock stretching. The VHDL code you posted has quite a lot of information about how to use so re-read that.
Alternatively take to question to Electrical Engineering Stack Exchange and take some oscilloscope readings of SDA/SCL.
I have been using FRDM_KL46Z development board to do some IR communication experiment. Right now, I got two PWM outputs with same setting (50% duty cycle, 38 kHz) had different voltage levels. When both were idle, one was 1.56V, but another was 3.30V. When the outputs were used to power the same IR emitter, the voltages were changed to 1.13V and 2.29V.
And why couldn't I use one PWM output to power two IR emitters at the same time? When I tried to do this, it seemed that the frequency was changed, so two IR receivers could not work.
I am not an expert in freescale, but how are you controlling your pwm? I'm guessing each pwm comes from a separate timer, maybe they are set up differently. Like one is in 16 bit mode (the 3.3V) and the other in 32 (1.56v) in that case even if they have the same limit in the counter ((2^17 - 1) / 2) would be 50% duty cycle of a 16 bit timer. But in a 32 bit, that same value would only be 25% duty so, one output would be ~1/2 the voltage of the other. SO I suggest checking the timer setup.
The reason the voltage changed is because the IR emmiters were loading the circuit. In an ideal situation this wouldn't happen, but if a source is giving too much current the voltage usually drops a bit.
I recently bought myself a Zybo Zync-7000 dev board so I could do some schoolwork & fiddling around with it at home, but when I was going to pick out my clock out of my UCF for the first time I came across this.
## Clock signal
#NET "clk" LOC=L16 | IOSTANDARD=LVCMOS33; #IO_L11P_T1_SRCC_35
#NET "clk" TNM_NET = sys_clk_pin;
#TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 125 MHz HIGH 50%;
I know I probably just have to take the first line to get my clk signal working but what is the rest for? Or am I mistaken and do I need all of it?
We got different hardware back in school and its a bit more straightforward there.
Thanks in advance.
I assume you are using ISE and not the new Vivado since only ISE uses UCF constraint files.
## Clock signal
This line is a comment about what the following lines pertain to.
#NET "clk" LOC=L16 | IOSTANDARD=LVCMOS33; #IO_L11P_T1_SRCC_35
This line specifies which physical pin (LOC=L16) on the FPGA the clock input (the input net named "clk" in the VHDL top level) from off-chip is connected to. It also specifies that the signal uses low voltage CMOS 3.3v signaling.
#NET "clk" TNM_NET = sys_clk_pin;
This just assigns a timing name to the net. For timing specific constraints, the timing name will be used instead of the (VHDL internal) net name.
#TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 125 MHz HIGH 50%;
This specifies that the timing of "sys_clk_pin" (resolves to the VHDL net "clk") should have a frequency of 125 MHz and a duty cycle of 50%. The tool needs to know this to determine how to route the signals without violating flip flop setup or hold times. The name "TS_sys_clk_pin" is just an identifier for this particular constraint.
Properly constraining a design is very important when you are near to filling up a part or if you want to run it at a higher clock speed. You can find a great wealth of information in the Xilinx constraint guide for ISE: https://www.xilinx.com/content/dam/xilinx/support/documents/sw_manuals/xilinx14_7/cgd.pdf
If you don't give your design timing constraints, the tools will typically throw a warning about the lack of constraints and it will tell you how fast you can run it at the end without causing errors. Timing constraints for the clocks are the most important. You typically only need other timing constraints on synchronous inputs and cross clock boundaries.
Note that all 4 lines are, in fact, currently commented out (prepended with a #). If you want to use the 3 functional lines, you need to remove the comment designation.