I just practicing a basic program in VHDL and keep getting three errors and don't seem to get a solution to them. The three errors are :
10028 Can't resolve multiple constant drivers for net "O" at question4.vhd(16)
10029 Constant driver at question4.vhd(15)
12153 Can't elaborate top-level user hierarchy
The code I used:
library IEEE;
use IEEE.std_logic_1164.all
entity question4 is
port(
E : in std_logic;
I : in std_logic_vector(3 downto 0);
O : out std_logic);
end question4;
architecture st1 of question4 is
begin
O <= '0' when E = '0';
O <= I(0) or I(1) or ((not I(2)) and (not I(3))) when E = '1';
end st1;
The correct syntax is the following:
library IEEE;
use IEEE.std_logic_1164.all
entity question4 is
port(
E : in std_logic;
I : in std_logic_vector(3 downto 0);
O : out std_logic);
end question4;
architecture st1 of question4 is
begin
O <= I(0) or I(1) or ((not I(2)) and (not I(3))) when E = '1' else '0';
end st1;
Related
Hi pleople this is my code, and the only error is Error (10028): Can't resolve multiple constant drivers for net "D[22]" at bonus2.vhd(26). I<m new at this and I don't understant this error.
Here is my code
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity bonus2 is
port (
B,C : in unsigned(15 downto 0);
clear, clk : in std_logic;
Q : out unsigned(31 downto 0)
);
end entity bonus2;
architecture arch_bonus2 of bonus2 is
signal mult : unsigned(31 downto 0); --signal d'addition
signal D: unsigned(31 downto 0); --signal d'addition
begin
mult <= B * C;
process(clear)
begin
if clear = '1' then
D <= x"00000000";
end if;
end process;
process(clk)
begin
if rising_edge(clk) then
D <= mult + D;
end if;
end process;
Q <= D;
end architecture arch_bonus2;
Your code shows that you might be unfamiliar with some concepts of hardware design, so I suggest you catch up on combinational/sequential logic and how to describe them with VHDL. Also, a good rule of thumb is that you should be able to draw some parts of your design, and if you do you'll see that the D wire is driven by multiple nets.
What I believe you want to do, based on your code, is to be able to reset/initialize your output register. However, the way you have coded it suggests you want an asynchronous reset.
Please check here to know more about synch vs asynch logic and then I suggest you to explore further to understand the implications.
Here is a modified version of your code with an asynchronous reset, because it seems what you want.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity bonus2 is
port (
B,C : in unsigned(15 downto 0);
clear, clk : in std_logic;
Q : out unsigned(31 downto 0)
);
end entity bonus2;
architecture arch_bonus2 of bonus2 is
signal mult : unsigned(31 downto 0); --signal d'addition
signal D: unsigned(31 downto 0); --signal d'addition
begin
mult <= B * C;
process(clk,clear)
if clear == '1' then
D <= x"00000000";
elsif rising_edge(clk) then
D <= mult + D;
end if;
end process;
Q <= D;
end architecture arch_bonus2;
I was trying to do a work and this error is boring me, i pass to a new project teste.vhdl and this keep happening, i need to have two barriers of clock one for input and another to output, to use timequest with combinational logic.
The 'and' is just a example.
library ieee;
use ieee.std_logic_1164.all;
--use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
ENTITY teste IS
PORT(
clock : in std_logic;
clear : in std_logic;
a : in std_logic_vector(3 downto 0);
b : in std_logic_vector(3 downto 0);
s : out std_logic_vector(3 downto 0)
);
END teste;
ARCHITECTURE comportamento OF teste IS
signal a1,b1,s1 : std_logic_vector(3 downto 0);
begin
FF_in: process(clock.clear)
begin
if clear = '1' then
a1 <= "0000";
b1 <= "0000";
elsif clock'event and clock = '1' then
a1 <= a;
b1 <= b;
end if;
end process;
s1 <= a1 and b1;
FF_out: process(clock.clear)
begin
if clear = '1' then
s <= "0000";
elsif clock'event and clock = '1' then
s <= s1;
end if;
end process;
END comportamento;
You have used a . Rather than , in the process sensitivity list. Using a . Is trying to access a record field.
So I've been working on some homework for my VHDL course and I can't seem to understand this problem.
The point here is to create the adder/subtractor of an ALU that works both on 2's complement and unsigned 32-bit buses, which is why I have a condition called sub_mode ( A - B = A + !B + 1 ) which will also be the carry-in when activated.
The rest of the different inputs and outputs are pretty self-explanatory.
My problem is with the testbenching of such component where, even though carry_temp and r_temp have been initialized in declaration section of the architecture, end up showing up undefined. I have guessed that it is due to the for loop within the process screwing everything up. Would that be an accurate guess? And if yes, is it possible to proceed to add two bit buses together without having to fully create an n-bit adder made from n 1-bit adder components?
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity add_sub is
port(
a : in std_logic_vector(31 downto 0);
b : in std_logic_vector(31 downto 0);
sub_mode : in std_logic;
carry : out std_logic;
zero : out std_logic;
r : out std_logic_vector(31 downto 0)
);
end add_sub;
architecture synth of add_sub is
signal cond_inv : std_logic_vector(31 downto 0);
signal carry_temp : std_logic_vector(32 downto 0) := (others => '0');
signal r_temp : std_logic_vector(31 downto 0) := (others => '0');
begin
behave : process(a,b,sub_mode)
begin
if sub_mode = '1' then
cond_inv <= b xor x"ffffffff";
else
cond_inv <= b;
end if;
carry_temp(0) <= sub_mode;
for i in 0 to 31 loop
r_temp(i) <= a(i) xor cond_inv(i) xor carry_temp(i);
carry_temp(i+1) <=
(a(i) and cond_inv(i)) or
(a(i) and carry_temp(i)) or
(cond_inv(i)and carry_temp(i));
end loop;
if r_temp = x"00000000" then
zero <= '1';
else
zero <= '0';
end if;
r <= r_temp;
carry <= carry_temp(32);
end process behave;
end synth;
I am trying to run my 3 to 7 decoder using the inputs coming from my counter ,all the individual codes run fine but the structural code is giving up some error
This is the program for my counter
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity counter is
port(clk , CLR : in std_logic;
Q : out std_logic_vector(2 downto 0) );
end counter;
architecture archi of counter is
signal tmp: std_logic_vector(2 downto 0);
begin
process (clk, CLR)
begin
if (CLR='1') then
tmp <= "000";
elsif (clk'event and clk='1') then
tmp <= tmp + 1;
end if;
end process;
Q <= tmp;
end archi;
this is the program for the decoder:
library IEEE;
use IEEE.std_logic_1164.all;
entity led_inp is
port (I : in std_logic_vector(2 downto 0) ;
L : out std_logic_vector(6 downto 0) ) ;
end led_inp ;
architecture led_inp1 of led_inp is
Begin
L(0) <= (not I(0)) and (not I(1)) and (not I(2));
L(1) <= (not I(0)) and (not I(1)) and I(2);
L(2) <= (not I(0)) and I(1) and (not I(2));
L(3) <= (not I(0)) and I(1) and I(2);
L(4) <= I(0) and (not I(1)) and (not I(2));
L(5) <= I(0) and (not I(1)) and I(2);
L(6) <= I(0) and I(1) and (not I(2));
end led_inp1;
this is the structural format for the whole design:
library IEEE;
use IEEE.std_logic_1164.all;
-- the entity of the whole design block, here i have given the names of the ports as the ones which i have used in my individual components
entity led_design is
port(clock,CLEAR :in std_logic;
L :out std_logic_vector(6 downto 0));
end led_design;
architecture led_design1 of led_design is
-- declaring my counter as a component
component counter
port(clk, CLR : in std_logic;
Q : out std_logic_vector(2 downto 0) );
end component ;
-- declaring my decoder as a component
component led_inp
port (I : in std_logic_vector(2 downto 0) ;
L : out std_logic_vector(6 downto 0)) ;
end component ;
signal I:std_logic_vector(2 downto 0);
begin
-- The PORT MAPPING BEGINS
L1: counter port map(clk=>clock,CLR=>CLEAR,I(2)=>I(2),I(1)=>I(1),I(0)=>I(0));
L2: led_inp port map(I(2)=>I(2),I(1)=>I(1),I(0)=>I(0),L(0)=>L(0),L(1)=>L(1),L(2)=>L(2),L(3)=>L(3),L(4)=>L(4),L(5)=>L(5),L(6)=>L(6));
L1: counter port
map(clk=>clock,CLR=>CLEAR,I(2)=>h(2),I(1)=>h(1),I(0)=>h(0));
end led_design1;
this is the error which comes up :ERROR
ncvhdl_p: *E,FMLBAD (led_count,85|44): poorly formed formal part of element association 87[4.3.3.2] 93[4.3.2.2].
errors: 1, warnings: 0"
Note the symbol led_count does not show up in your VHDL design description, is that the file name?
You have two labels L1 in led_design, it's also missing a declaration for signal h to match signal I. (which also tells you it's not used anywhere else).
Both counter association lists (port maps) don't match the component declaration. After fixing those things your code analyzes. note h isn't used anywhere else.
Read the Markdown help to learn how to format code, it's awful.
The lack of proper formatting and the inability to understand the error is preventing those who could answer from providing an answer.
Try this:
library IEEE;
use IEEE.std_logic_1164.all;
--use IEEE.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity counter is
port(clk , CLR : in std_logic;
Q : out std_logic_vector(2 downto 0) );
end counter;
architecture archi of counter is
signal tmp: std_logic_vector(2 downto 0);
begin
process (clk, CLR)
begin
if (CLR='1') then
tmp <= "000";
elsif (clk'event and clk='1') then
tmp <= std_logic_vector(unsigned(tmp) + 1);
end if;
end process;
Q <= tmp;
end archi;
library IEEE;
use IEEE.std_logic_1164.all;
entity led_inp is
port (I : in std_logic_vector(2 downto 0) ;
L : out std_logic_vector(6 downto 0) ) ;
end led_inp ;
architecture led_inp1 of led_inp is
Begin
L(0) <= (not I(0)) and (not I(1)) and (not I(2));
L(1) <= (not I(0)) and (not I(1)) and I(2);
L(2) <= (not I(0)) and I(1) and (not I(2));
L(3) <= (not I(0)) and I(1) and I(2);
L(4) <= I(0) and (not I(1)) and (not I(2));
L(5) <= I(0) and (not I(1)) and I(2);
L(6) <= I(0) and I(1) and (not I(2));
end led_inp1;
library IEEE;
use IEEE.std_logic_1164.all;
entity led_design is
port(clock,CLEAR :in std_logic;
L :out std_logic_vector(6 downto 0));
end led_design;
architecture led_design1 of led_design is
component counter
port(clk, CLR : in std_logic;
Q : out std_logic_vector(2 downto 0) );
end component ;
component led_inp
port (I : in std_logic_vector(2 downto 0) ;
L : out std_logic_vector(6 downto 0)) ;
end component ;
signal I:std_logic_vector(2 downto 0);
signal h:std_logic_vector(2 downto 0);
begin
L1: counter port map (
clk=>clock,CLR=>CLEAR, Q => I); -- I(2)=>I(2),I(1)=>I(1),I(0)=>I(0));
L2: led_inp port map ( I(2)=>I(2),I(1)=>I(1),I(0)=>I(0),L(0)=>L(0),L(1)=>L(1),L(2)=>L(2),L(3)=>L(3),L(4)=>L(4),L(5)=>L(5),L(6)=>L(6));
L3: counter port map( clk=>clock,CLR=>CLEAR, Q => h);-- I(2)=>h(2),I(1)=>h(1),I(0)=>h(0));
-- ERROR
--**ncvhdl_p: *E,FMLBAD (led_count,85|44): poorly formed formal part of element association 87[4.3.3.2] 93[4.3.2.2].
-- errors: 1, warnings: 0"**
end led_design1;
The use clause for numeric_std and the type conversions is to enable me to use a -1993 compliant tool (which doesn't have std_logic_unsigned). Those changes are likely not required in your environment.
Notice the output of the second counter (connected to h) now labelled L3 does not go anywhere.
Notice the error should also show up in your line 83 if you simply fix line 85.
How can I make a testbench for this full adder code. I'm a newbie and would appreciate any help.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Full_Adder is
PORT(a , b , C_In : IN STD_LOGIC; S,C_Out : OUT STD_LOGIC);
end Full_Adder;
architecture Behavioral of Full_Adder is
begin
S <= a XOR b XOR C_In;
C_Out <= (a AND b) OR (a AND C_In) OR (b AND C_In);
end Behavioral;
Here's a good reference, one of the first that came up when I googled how to write a testbench.
You should google first, give it an honest shot, then come back here with more specific questions.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Full_Adder_tb is
end Full_Adder_tb;
architecture Behavioral of Full_Adder_tb is
component Full_Adder is -- component declaration
port(
a : in std_logic;
b : in std_logic;
C_in : in std_logic;
S : out std_logic;
C_out : out std_logic
);
end component;
signal a: std_logic := '0'; -- signal declarations
signal b: std_logic := '0';
signal C_in: std_logic := '0';
signal S: std_logic;
signal C_out : std_logic;
begin
uut : Full_Adder -- component instantiation
port map(
a => a, -- signal mappings
b => b,
C_in => C_in,
S => S,
C_out => C_out);
process
begin
wait 10 ns; -- wait time
a <= '0'; b <= '0'; C_in <= '1'; -- example test vector
wait 10 ns;
-- Other test vectors and waits here
end process;
end Behavioral;