data changes with clock - vhdl

Question

i am new in the fpga filed ,
im trying to sample 2 inputs that rises with clock at the same time.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith;
use ieee.numeric_std.all;
ENTITY hold_threat IS
PORT (
pwr_gt_thresh : IN std_logic;
clk : IN std_logic;
reset : IN std_logic;
hw_seperation_bin_number : in std_logic_vector(12 downto 0);
fft_raw_index : in std_logic_vector (12 downto 0);
fft_data_valid : in std_logic;
threat_exists_buffered_pulse : out std_logic;
pwr_gt_thresh_out : out std_logic;
threat_end_index :out std_logic_vector (12 downto 0);
threat_start_index :out std_logic_vector (12 downto 0)
);
END hold_threat;
ARCHITECTURE behavoral OF hold_threat IS
signal s_threat_exists_buffered_pulse : std_logic;
signal s_pwr_gt_thresh_out : std_logic;
signal hw_seperation_bin_number_counter : integer range 0 to 8191;
signal s_fft_start_index : std_logic_vector (13 downto 0);
signal s_fft_end_index : std_logic_vector (12 downto 0);
signal s_new_count : std_logic;
begin
threat_start_index <= s_fft_start_index(12 downto 0);
threat_end_index <= s_fft_end_index;
threat_exists_buffered_pulse <= s_threat_exists_buffered_pulse;
pwr_gt_thresh_out <= s_pwr_gt_thresh_out;
process(reset, clk)
begin
if reset = '1' then
hw_seperation_bin_number_counter <= to_integer(unsigned(hw_seperation_bin_number)) -1 ;
s_threat_exists_buffered_pulse <= '0';
s_fft_start_index <="11" & X"FFF";
s_fft_end_index <= '1' & X"FFF";
s_new_count <= '0' ;
elsif rising_edge(clk) then
if(fft_data_valid = '1') then
if (pwr_gt_thresh = '1' ) then
hw_seperation_bin_number_counter <= to_integer(unsigned(hw_seperation_bin_number)) -1;
s_new_count <='1';
s_threat_exists_buffered_pulse <= '1';
if(s_fft_start_index(13) = '1' ) then
s_fft_start_index<= '0'& fft_raw_index;
else
s_fft_start_index<= s_fft_start_index;
end if;
else
if( hw_seperation_bin_number_counter = 0 ) and s_new_count ='1'then
s_threat_exists_buffered_pulse <= '0';
s_fft_end_index<= fft_raw_index;
s_new_count <= '0';
elsif (s_new_count ='1') then
hw_seperation_bin_number_counter <= hw_seperation_bin_number_counter - 1;
s_threat_exists_buffered_pulse <= '1';
end if;
end if;
else -- clock , no data valid
s_threat_exists_buffered_pulse <= s_threat_exists_buffered_pulse;
if (s_new_count = '0') then
hw_seperation_bin_number_counter <= to_integer(unsigned(hw_seperation_bin_number)) -1 ;
s_fft_start_index <="11" & X"FFF";
s_fft_end_index <= '1' & X"FFF";
else
hw_seperation_bin_number_counter <= hw_seperation_bin_number_counter;
s_fft_start_index <=s_fft_start_index;
s_fft_end_index <= s_fft_end_index;
end if;
end if;
end if;
end process;
END ARCHITECTURE behavoral;
in the simulation the clock ,pwr_gt_thresh , fft_data_valid rise together at the same time but the condition
elsif rising_edge(clk) then
if(fft_data_valid = '1') then
if (pwr_gt_thresh = '1' ) then
is never true .
if i change the simulation so that the data rise before the clock everything works good
why the data and the clock cannot rise together ?

Answer 1

Disclaimer: For more complete details you might want to do some research on "setup time" for clocked logic. And while you're at it, keep reading on "hold time".
In just three sentences:
The signal on a sampled data line needs to fulfill some timing requirements to be "caught" correctly. The time before the clock edge is the setup time. The time the signal has to be stable is the hold time.
Something to think about for fun:
You will come across values of real hardware that specify negative setup times. Was does this mean?