cant understand this.. tried different types for the buffers and nothing works the title says it.
im trying to make a dc motor control and the buffer variabls cant work with the "<=" operator for some reason
library ieee;
use ieee.std_logic_1164.all;
entity PWM_Ctrl is
port(PWM_1KHz: in std_logic;
Ma0: in bit;
Ma1: in bit;
Mb0: in bit;
Mb1: in bit;
LwheelF: buffer bit;
LwheelB: buffer bit;
RwheelF: buffer bit;
RwheelB: buffer bit);
end;
architecture behave of PWM_Ctrl is
begin
process(PWM_1KHz,LwheelF,LwheelB)-- left wheel
begin
if Ma0 = '0' and Ma1 = '0' then LwheelF <= '0' and LwheelB <= '0'; end if; -- No movement
if Ma0 = '0' and Ma1 = '1' then LwheelF <= '1' and LwheelB <= '0'; end if; -- Forward
if Ma0 = '1' and Ma1 = '0' then LwheelF <= '0' and LwheelB <= '1'; end if; -- backward
if Ma0 = '1' and Ma1 = '1' then LwheelF <= '0' and LwheelB <= '0'; end if; -- No movement
end process;
process(PWM_1KHz,RwheelF,LwheelB) -- right wheel
begin
if Mb0 = '0' and Mb1 = '0' then RwheelF <= '0' and RwheelB <= '0'; end if; -- No movement
if Mb0 = '0' and Mb1 = '1' then RwheelF <= '1' and RwheelB <= '0'; end if; -- Forward
if Mb0 = '1' and Mb1 = '0' then RwheelF <= '0' and RwheelB <= '1'; end if; -- backward
if Mb0 = '1' and Mb1 = '1' then RwheelF <= '0' and RwheelB <= '0'; end if; -- No movement
end process;
end behave;
"<=" is the both assignment operator, and also the "less than or equals" operator. Your statement:
LwheelF <= '0' and LwheelB <= '0';
And similar all use it in "less than or equals" context. And they cannot be used here because there is no assignment.
I think you meant:
LwheelF <= '0';
LwheelB <= '0';
etc
Related
I'm trying learning to code in VHDL and the below code gives me no errors when compiling but gives me a latching warning. I need to get rid of this latch as I believe it is causing me problems in my next piece of code which will use this (8x8 multiplier).
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
ENTITY control IS
PORT (
clk, reset_a, start : IN STD_LOGIC;
count : IN UNSIGNED (1 DOWNTO 0);
input_sel, shift_sel : OUT UNSIGNED(1 DOWNTO 0);
state_out : OUT UNSIGNED(2 DOWNTO 0);
done, clk_ena, sclr_n : OUT STD_LOGIC
);
END ENTITY control;
ARCHITECTURE logic OF control IS
type logic_state is (idle, lsb, mid, msb, calc_done, err);
signal current_state: logic_state;
signal next_state: logic_state;
BEGIN
PROCESS (clk, reset_a)
BEGIN
if reset_a = '1' then
current_state <= idle;
elsif rising_edge (clk) then
current_state <= next_state;
end if;
END PROCESS;
PROCESS (current_state, start, count)
BEGIN
CASE current_state IS
when idle =>
if start = '1' then
next_state <= lsb;
else
next_state <= idle;
end if;
when lsb =>
if start = '0' and count = "00" then
next_state <= mid;
else
next_state <= err;
end if;
when mid =>
if start = '0' then
if (count = "01") then
next_state <= mid;
elsif (count = "10") then
next_state <= msb;
else
next_state <= err;
end if;
end if;
when msb =>
if start = '0' then
if (count = "11") then
next_state <= calc_done;
else
next_state <= err;
end if;
end if;
when calc_done =>
if start = '0' then
next_state <= idle;
else
next_state <= err;
end if;
when err =>
if start = '1' then
next_state <= lsb;
else
next_state <= err;
end if;
END CASE;
END PROCESS;
mealy: PROCESS (current_state, start, count)
BEGIN
input_sel <= "00";
shift_sel <= "00";
done <= '0';
clk_ena <= '0';
sclr_n <= '1';
CASE current_state IS
when idle =>
if start = '1' then
sclr_n <= '0';
clk_ena <= '1';
END IF;
when lsb =>
if start = '0' and count = "00" then
sclr_n <= '1';
end if;
when mid =>
if start = '0' then
if (count = "01") then
input_sel <= "01";
shift_sel <= "01";
elsif (count = "10") then
input_sel <= "10";
shift_sel <= "01";
end if;
end if;
when msb =>
if start = '0' then
if (count = "11") then
input_sel <= "11";
shift_sel <= "10";
end if;
end if;
when calc_done =>
if start = '0' then
input_sel <= "00";
shift_sel <= "00";
done <= '1';
clk_ena <= '0';
end if;
when err =>
if start = '1' then
input_sel <= "00";
shift_sel <= "00";
done <= '0';
clk_ena <= '1';
sclr_n <= '0';
end if;
END CASE;
END PROCESS mealy;
moore: PROCESS(current_state)
BEGIN
state_out <= "000";
CASE current_state IS
WHEN idle =>
WHEN lsb =>
state_out <= "001";
WHEN mid =>
state_out <= "010";
WHEN msb =>
state_out <= "011";
WHEN calc_done =>
state_out <= "100";
WHEN err =>
state_out <= "101";
END CASE;
END PROCESS moore;
END ARCHITECTURE logic;
I get the following warning:
Warning (10631): VHDL Process Statement warning at mult_control.vhd(65): inferring latch(es) for signal
or variable "next_state", which holds its previous value in one or more paths through the process
That points to this node (line 33):
PROCESS (current_state, start, count)
And that warning leads to other warnings (for every type .idle, .mid, .msb, etc.):
Warning (13012): Latch next_state.idle_218 has unsafe behavior
Warning (13013): Ports D and ENA on the latch are fed by the same signal start
Thank you!
line 33 is in the second process (with no label).
Why are there inferred latches?
See IEEE Std 1076.6-2004 (withdrawn) RTL Synthesis
6.2.1.1 Level-sensitive storage from process with sensitivity list
A level-sensitive storage element shall be modeled for a signal (or variable) when all the following apply:
a) The signal (or variable) has an explicit assignment.
b) The signal (or variable) does not have an execution path with as a condition.
c) There are executions of the process that do not execute an explicit assignment (via an assignment statement) to the signal (or variable).
By default, the effect of an identity assignment of the signal (or variable) shall be as though the assignment was not present.
If the combinational attribute decorates the signal (or variable), combinational logic with feedback shall be synthesized.
To avoid unintentional latches as condition c) has to be invalid.
An example in the question code that can cause latches:
when msb =>
if start = '0' then
if (count = "11") then
next_state <= calc_done;
else
next_state <= err;
end if;
end if;
This is missing an else for the outer if statement and meets rule c) quoted above. That can be cured:
when msb =>
if start = '0' then
if (count = "11") then
next_state <= calc_done;
else
next_state <= err;
end if;
else -- now all binary values of start in state msb assign next_state
next_state <= msb;
end if;
You can assign a value to a target before an if statement that otherwise meets c):
when msb =>
next_state <= msb; -- not always assigned in the if statement
if start = '0' then
if (count = "11") then
next_state <= calc_done;
else
next_state <= err;
end if;
end if;
In a sequence of statements the 'default' assignment occurs unless overwritten by a subsequent assignment in the if statement.
The question's code has other occurrences of c) issues (including in other processes) that can be similarly treated.
I am trying to simulate an elevator and as a result i get the error
ERROR:Xst:827 = Signal count cannot be synthesized, bad synchronous description
I am following the code from this source [https://www.youtube.com/watch?v=i03_-NMwmDs] since mine is very similar,(i have 7 floors and two more elevators). At first i am working with the code mentioned on the video and later i am going to implement two more elevators to work together in this simulation.
Thanks in advance.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity elevator is
port (clk: in std_logic;
sensors1: out std_logic:='0'; --sensors at each level for elevator 1
a1, a2, a3, a4, a5, a6, a7: out std_logic; -- for LED display at FPGA
insideopendoor, in1, in2, in3, in4, in5, in1up, in2up, in3up, in4up, in5up, in5down, in4down, in3down, in2down, in1down: std_logic; -- input request for each floor
opendoor: out std_logic; -- from inside elevator
closedoor: out std_logic); -- from inside elevator
end elevator;
architecture sequence of elevator is
constant timedoorclose: integer := 3;
constant timedoorclosed: integer := 2;
constant time_nx_state: integer :=4;
signal demand: std_logic_vector(0 to 4) := "00000";
signal direction_of_elevator : integer range 0 to 2 := 0;
signal updownpassenger : std_logic := '0';
signal signalstatus: std_logic := '1';
type status is (L1, L2, L3, L4, L5);
signal pr_state, nx_state: status;
begin
main: process (clk, insideopendoor, in1, in2, in3, in4, in5, in1up, in2up, in3up, in4up, in5up, in5down, in4down, in3down, in2down, in1down)
variable digit1 : std_logic_vector (6 downto 0);
variable count : integer range 0 to (time_nx_state + timedoorclose + timedoorclosed);
variable bufferopendoor : std_logic;
variable position : integer range 0 to 4;
variable tempup : integer range 1 to 2 := 1;
variable tempdown : integer range -4 to 4;
begin
if (clk'event and clk='1') then
demand(0) <= demand(0) or in1 or in1up or in1down;
demand(1) <= demand(1) or in2 or in2up or in2down;
demand(2) <= demand(2) or in3 or in3up or in3down;
demand(3) <= demand(3) or in4 or in4up or in4down;
demand(4) <= demand(4) or in5 or in5up or in5down;
case pr_state is
when L1 => position := 0;
when L2 => position := 1;
when L3 => position := 2;
when L4 => position := 3;
when L5 => position := 4;
end case;
for i in 1 to 4 loop
if demand(i) ='1' then
tempup := i - position;
else null;
end if;
end loop;
for i in 3 downto 0 loop
bufferopendoor := '1';
closedoor <= '0';
count := 0;
end loop; --
elsif (updownpassenger = '1') then
if (count < timedoorclose) then
opendoor <= '1';
bufferopendoor := '1';
elsif count < (timedoorclose + timedoorclosed) then
opendoor <= '0';
bufferopendoor := '0';
else
closedoor <= '0';
end if;
--else null; ------
--end if; ------
-----------part main-----------------
count := count +1;
if insideopendoor = '1' then
opendoor<='1';
bufferopendoor :='1';
closedoor <= '0';
count := 0;
elsif (updownpassenger ='1') then
if (count < timedoorclose) then
opendoor <= '1';
bufferopendoor := '1';
closedoor <= '0';
elsif (count < (timedoorclose + timedoorclosed)) then
opendoor <= '0';
bufferopendoor := '0';
closedoor <= '1';
else
closedoor <= '0';
pr_state <= nx_state;
if signalstatus = '1' then
signalstatus <= '0';
else
signalstatus <= '1';
end if;
count := 0;
end if;
else null; --
end if;--
case nx_state is
when L1 =>
digit1 := "1111001";
if demand(0) = '1' then
demand(0) <= '0';
else null;
end if;
when L2 =>
digit1 := "0100100";
if demand(1) = '1' then
demand(1) <= '0';
else null;
end if;
when L3 =>
digit1 := "0110000";
if demand(3) = '1' then
demand(3) <= '0';
else null;
end if;
when L4 =>
digit1 := "0011001";
if demand(3) = '1' then
demand(3) <= '0';
else null;
end if;
when L5 =>
digit1 := "0010010";
if demand(4) = '1' then
demand(4) <= '0';
else null;
end if;
when others => null;
end case;
a1 <= digit1(0);
a2 <= digit1(1);
a3 <= digit1(2);
a4 <= digit1(3);
a5 <= digit1(4);
a6 <= digit1(5);
a7 <= digit1(6);
end if;
end process main;
step: process (pr_state, signalstatus)
begin
case pr_state is
--end if;
when L1 =>
if (demand(0)='1') then
nx_state <= pr_state;
updownpassenger <= '1';
else
updownpassenger <= '0';
if direction_of_elevator = 1 then
nx_state <=L2;
elsif direction_of_elevator = 2 then
nx_state <= pr_state;
else
nx_state <= pr_state;
end if;
end if;
when L2 =>
if (demand(1)= '1') then
nx_state <= pr_state;
updownpassenger <= '1';
else
updownpassenger <= '0';
if direction_of_elevator = 1 then
nx_state <= L3;
elsif direction_of_elevator = 2 then
nx_state <= L1;
else
nx_state <= pr_state;
end if;
end if;
when L3 =>
if (demand(2)= '1') then
nx_state <= pr_state;
updownpassenger <= '1';
else
updownpassenger <= '0';
if direction_of_elevator = 1 then
nx_state <= L4;
elsif direction_of_elevator = 2 then
updownpassenger <= '1';
else
updownpassenger <= '0';
if direction_of_elevator = 1 then
nx_state <= L5;
elsif direction_of_elevator = 2 then
end if;
end if;
end if;
when L5 =>
if (demand(4)='1') then
nx_state <= pr_state;
updownpassenger <= '1';
else
updownpassenger <= '0';
if direction_of_elevator = 1 then
nx_state <= L4;
elsif direction_of_elevator = 2 then
nx_state <= L1;
else
nx_state <= pr_state;
end if;
end if;
when others => null;
end case;
end process step;
end sequence;
Your code seems very mixed up. There is a specific reason why it won't synthesise: think carefully when the code immediately following this line here
elsif (updownpassenger = '1') then
will be executed. It will be executed following a positive edge or negative edge on any input in the sensitivity list, apart from clk where it will be executed only following a negative edge. How would you design logic with such behaviour? Well, your synthesiser can't do it, either.
Basically, you need to refactor your code. You need to split it into sequential and combinational processes. (Combinational logic is logic whose output depends only on it's input and thus is logic that contains no latches or flip-flops. Sequential logic is logic that contains latches or flip-flops, but will also usually contain some gates too. Do not use latches - they are not synchronous design.) Whilst there are many ways to code such processes, it is wise to be consistent by sticking to a template. Here are three templates, which if followed, will give you everything you need and will keep your VHDL coding life simple:
Here is the template for sequential logic with an asynchronous reset, which all synthesis tools should understand:
process(clock, async_reset) -- nothing else should go in the sensitivity list
begin
-- never put anything here
if async_reset ='1' then -- or '0' for an active low reset
-- set/reset the flip-flops here
-- ie drive the signals to their initial values
elsif rising_edge(clock) then -- or falling_edge(clock) or clk'event and clk='1' or clk'event and clk='0'
-- put the synchronous stuff here
-- ie the stuff that happens on the rising or falling edge of the clock
end if;
-- never put anything here
end process;
Here is the template for sequential logic without an asynchronous reset:
process(clock) -- nothing else should go in the sensitivity list
begin
-- never put anything here
if rising_edge(clock) then -- or falling_edge(clock) or clk'event and clk='1' or clk'event and clk='0'
-- put the synchronous stuff here
-- ie the stuff that happens on the rising or falling edge of the clock
end if;
-- never put anything here
end process;
And here is the corresponding template for a combinational process:
process(all inputs in the sensitivity list) -- an 'input' is a signal either on the LHS of an assignment or a signal that is tested
begin
-- combinational logic (with complete assignment and no feedback)
end process;
sorry for my weak english .
I want to write a VHDL code of simple Control unit or TPG controller that produce a signal like S2 , that motivated from FSM which count two rising edge of clock and then make the s2=1, so I want help to write a code wich count two rise edge then produce s2=1. then in third cycle make it zero.
here is my code that does not work :
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
USE ieee.std_logic_unsigned.all ;
ENTITY TPG_CONTROL IS
PORT ( Clock : IN STD_LOGIC ;
TPG_CONTROL_En : IN STD_LOGIC ;
--reset : IN STD_LOGIC ;
ST2 : OUT STD_LOGIC ) ;
END TPG_CONTROL ;
ARCHITECTURE behav OF TPG_CONTROL IS
SIGNAL Count : std_logic_vector(1 DOWNTO 0) := "00" ;
TYPE state IS (S0, S1, S2);
SIGNAL Moore_state: state;
SIGNAL Clear: std_logic ;
begin
U_Moore0: PROCESS (clock, Clear, TPG_CONTROL_En, Count)
BEGIN
IF(Count = "11") THEN
Moore_state <= S0;
Clear <= '1';
ELSIF ( (rising_edge (clock)) AND TPG_CONTROL_En= '1') THEN
-- IF (Count = "11") THEN Clear <= '1' THEN
IF Clear = '1' THEN
Count <= "00" ;
ELSE
Count <= Count + 1 ;
-- END IF ;
-- END IF;
-- END IF;
-- END IF;
CASE Moore_state IS
WHEN S0 =>
IF Count = "01" THEN
Moore_state <= S1;
-- ELSE
-- Moore_state <= S0;
END IF;
WHEN S1 =>
IF Count = "10" THEN
Moore_state <= S2;
-- ELSE
-- Moore_state <= S1;
END IF;
WHEN S2 =>
IF Count = "11" THEN
Moore_state <= S0;
-- ELSE
-- Moore_state <= S1;
END IF;
END CASE;
END IF;
END IF;
--ST2 <= ‘1’ WHEN Moore_state = S2 ELSE ‘0’;
END PROCESS;
U_Moore1: PROCESS (clock, TPG_CONTROL_En)
BEGIN
IF ( (rising_edge (clock)) AND TPG_CONTROL_En= '1') THEN
IF ( Moore_state = S2 ) THEN ST2 <= '1' ;
ELSE ST2 <= '0' ;
END IF;
END IF;
END PROCESS;
END behav ;
Fixing the back ticks in you're comment:
Was:
--ST2 <= ‘1’ WHEN Moore_state = S2 ELSE ‘0’;
Is:
-- st2 <= '1' when moore_state = s2 else '0';
Your code analyzes and elaborates.
Writing a simple testbench:
library ieee;
use ieee.std_logic_1164.all;
entity tpg_control_tb is
end entity;
architecture foo of tpg_control_tb is
signal clk: std_logic := '0';
signal enab: std_logic := '1';
signal st2: std_logic;
begin
CLOCK:
process
begin
wait for 10 ns;
clk <= not clk;
if Now > 100 ns then
wait;
end if;
end process;
DUT:
entity work.tpg_control
port map (
clock => clk,
tpg_control_en => enab,
st2 => st2
);
end architecture;
with a constant tpg_control_en emonstrates the behavior to which you allude, that you aren't reaching S2.
If you comment out the asynchronous clear of moore_state by count:
u_moore0: process (clock, clear, tpg_control_en, count)
begin
if(count = "11") then
-- moore_state <= s0;
clear <= '1';
elsif ( (rising_edge (clock)) and tpg_control_en= '1') then
-- if (count = "11") then clear <= '1' then
if clear = '1' then
count <= "00" ;
else
count <= count + 1 ;
-- end if ;
-- end if;
-- end if;
-- end if;
case moore_state is
when s0 =>
if count = "01" then
moore_state <= s1;
-- else
-- moore_state <= s0;
end if;
when s1 =>
if count = "10" then
moore_state <= s2;
-- else
-- moore_state <= s1;
end if;
when s2 =>
if count = "11" then
moore_state <= s0;
-- else
-- moore_state <= s1;
end if;
end case;
end if;
end if;
-- st2 <= '1' when moore_state = s2 else '0';
end process;
You actually get there:
I'd suspect without knowing why you have an asynchronous clear that the process statement sensitivity list could be reduced to clock.
And because unsigned/std_logic_vector "+" rolls over you can simply the heck out of what you have:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity tpg_control is
port (
clock: in std_logic;
tpg_control_en: in std_logic;
--reset: in std_logic;
st2: out std_logic
);
end tpg_control;
architecture behav of tpg_control is
signal count : std_logic_vector(1 downto 0) := "00" ;
type state is (s0, s1, s2);
signal moore_state: state;
-- signal clear: std_logic;
begin
u_moore0:
process (clock)
begin
-- if(count = "11") then
-- moore_state <= s0;
-- clear <= '1';
-- elsif ...
if rising_edge(clock) and tpg_control_en = '1' then
-- if clear = '1' then
-- count <= "00" ;
-- else
count <= count + 1;
case moore_state is
when s0 =>
if count = "01" then
moore_state <= s1;
end if;
when s1 =>
if count = "10" then
moore_state <= s2;
end if;
when s2 =>
if count = "11" then
moore_state <= s0;
end if;
end case;
-- end if;
end if;
end process;
u_moore1:
process (clock)
begin
if rising_edge(clock) and tpg_control_en = '1' then
if moore_state = s2 then
st2 <= '1' ;
else st2 <= '0' ;
end if;
end if;
end process;
end behav ;
And this shows the state roll over:
Note that count and moore_state hold the same information in two different type formats. You don't actually need both. Generally synthesis tools would be capable of producing a working implementation from moore_state alone.
I was wondering why this doesn't work in my final design:
process (clk_in, reset, start)
begin
if (reset = '1') then
init_counter <= '0';
init_counter_done <= '0';
elsif rising_edge(clk_in) then
if (start = '1' and init_counter_done = '0') then
init_counter <= '1';
init_counter_done <= '1';
end if;
if (init_counter = '1') then
init_counter <= '0';
end if;
end if;
end process;
My idea is that when start changes state (from 0 to 1) init_counter should become 1 for one clock cycle. It doesn't seem to work though.
If you can tolerate the delay/latency, I would recommend a small adjustment as follows:
process (clk_in, reset)
begin
if (reset = '1') then
init_counter <= '0';
init_counter_done <= '0';
start_d <= '0';
elsif rising_edge(clk_in) then
start_d <= start;
if (start = '1' and start_d = '0' and init_counter_done = '0') then
init_counter <= '1';
init_counter_done <= '1';
else
init_counter <= '0';
end if;
end if;
end process;
This will keep your process purely synchronous. Previously it was slightly "confusing" (and possibly so to the tools) since "start" was in the sensitivity list, but your outputs would only update on the rising clock edge.
If this still doesn't work, can you clarify if it doesn't work in simulation or in hardware? If it does not work in hardware, possibly you need to debounce your start signal?
I want to detect the edges on the serial data signal (din). I have written the following code in VHDL which is running successfully but the edges are detected with one clock period delay i.e change output is generated with one clk_50mhz period delay at each edge. Could anyone please help me to detect edges without delay. Thank you.
process (clk_50mhz)
begin
if clk_50mhz'event and clk_50mhz = '1' then
if (rst = '0') then
shift_reg <= (others => '0');
else
shift_reg(1) <= shift_reg(0);
shift_reg(0) <= din;
end if;
end if;
end process;
process (clk_50mhz)
begin
if clk_50mhz'event and clk_50mhz = '1' then
if rst = '0' then
change <= '0' ;
elsif(clk_enable_2mhz = '1') then
change <= shift_reg(0) xor shift_reg(1);
end if ;
end if ;
end process ;
When I changed my code to following I am able to detect the edges
process (clk_50mhz)
begin
if clk_50mhz'event and clk_50mhz = '1' then
if (RST = '0') then
shift_reg <= (others=>'0');
else
shift_reg(1) <= shift_reg(0);
shift_reg(0) <= din;
end if;
end if;
end process;
change <= shift_reg(1) xor din;
Here you go
library ieee;
use ieee.std_logic_1164.all;
entity double_edge_detector is
port (
clk_50mhz : in std_logic;
rst : in std_logic;
din : in std_logic;
change : out std_logic
);
end double_edge_detector;
architecture bhv of double_edge_detector is
signal din_delayed1 :std_logic;
begin
process(clk_50mhz)
begin
if rising_edge(clk_50mhz) then
if rst = '1' then
din_delayed1 <= '0';
else
din_delayed1 <= din;
end if;
end if;
end process;
change <= (din_delayed1 xor din); --rising or falling edge (0 -> 1 xor 1 -> 0)
end bhv;
You have to use a combinatorial process to detect the difference without incurring extra clock cycle delays. (You will still need one register to delay the input as well.)
DELAY: process(clk_50mhz)
begin
if clk_50mhz'event and clk_50mhz = '1' then
din_reg <= din;
end if;
end process;
change <= din xor din_reg;