I want to detect the edges on the serial data signal (din). I have written the following code in VHDL which is running successfully but the edges are detected with one clock period delay i.e change output is generated with one clk_50mhz period delay at each edge. Could anyone please help me to detect edges without delay. Thank you.
process (clk_50mhz)
begin
if clk_50mhz'event and clk_50mhz = '1' then
if (rst = '0') then
shift_reg <= (others => '0');
else
shift_reg(1) <= shift_reg(0);
shift_reg(0) <= din;
end if;
end if;
end process;
process (clk_50mhz)
begin
if clk_50mhz'event and clk_50mhz = '1' then
if rst = '0' then
change <= '0' ;
elsif(clk_enable_2mhz = '1') then
change <= shift_reg(0) xor shift_reg(1);
end if ;
end if ;
end process ;
When I changed my code to following I am able to detect the edges
process (clk_50mhz)
begin
if clk_50mhz'event and clk_50mhz = '1' then
if (RST = '0') then
shift_reg <= (others=>'0');
else
shift_reg(1) <= shift_reg(0);
shift_reg(0) <= din;
end if;
end if;
end process;
change <= shift_reg(1) xor din;
Here you go
library ieee;
use ieee.std_logic_1164.all;
entity double_edge_detector is
port (
clk_50mhz : in std_logic;
rst : in std_logic;
din : in std_logic;
change : out std_logic
);
end double_edge_detector;
architecture bhv of double_edge_detector is
signal din_delayed1 :std_logic;
begin
process(clk_50mhz)
begin
if rising_edge(clk_50mhz) then
if rst = '1' then
din_delayed1 <= '0';
else
din_delayed1 <= din;
end if;
end if;
end process;
change <= (din_delayed1 xor din); --rising or falling edge (0 -> 1 xor 1 -> 0)
end bhv;
You have to use a combinatorial process to detect the difference without incurring extra clock cycle delays. (You will still need one register to delay the input as well.)
DELAY: process(clk_50mhz)
begin
if clk_50mhz'event and clk_50mhz = '1' then
din_reg <= din;
end if;
end process;
change <= din xor din_reg;
Related
Please forgive myself if you will find some trivial errors in my code .. I'm still a beginner with VHDL.
Well, I have to deal with a serial interface from an ADC. The interface is quite simple ... there is a wire for the serial data (a frame of 24 bits), a signal DRDY that tells me when the new sample data is available and a serial clock (SCLK) that push the bit into (rising edge). Everything is running continuously...
I need to capture correctly the 24 bit of the sample, put them on a parallel bus (shift register) and provide a "data valid" signal for the blocks that will process the samples ...
Due to the fact that my system clock is x4 the frequency of the serial interface, i was thinking that doing the job with a FSM will be easy ...
When you look into the code you will see a process to capture the rising edges of the DRDY and SCLK.
Then a FSM with few states (Init, wait_drdy, wait_sclk, inc_count, check_count).
I use a counter (cnt unsigned) to check if I've already captured the 24 bits, using also to redirect the states of the FSM in "check_count" state.
Here a picture:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity serial_ads1675 is
Port (
clk : in STD_LOGIC;
reset : in STD_LOGIC;
sclk : in std_logic;
sdata : in std_logic;
drdy : in std_logic;
pdata : out std_logic_vector(23 downto 0);
pdready : out std_logic
);
end serial_ads1675;
architecture Behavioral of serial_ads1675 is
-- Internal declarations
signal ipdata : std_logic_vector (23 downto 0);
signal ipdready : std_logic;
signal tmp1, tmp2, tmp3, tmp4 : std_logic;
signal rise_drdy, rise_sclk : std_logic;
signal cnt : unsigned (4 downto 0);
type state is (init, wait_drdy, wait_sclk, inc_count, check_count);
signal actual_state, next_state : state;
begin
-- Concurrent statements
pdata <= ipdata;
pdready <= ipdready;
rise_drdy <= '1' when ((tmp1 = '1') and (tmp2 = '0')) else '0';
rise_sclk <= '1' when ((tmp3 = '1') and (tmp4 = '0')) else '0';
-- Process
process (clk, reset)
begin
if(reset = '0') then
tmp1 <= '0';
tmp2 <= '0';
tmp3 <= '0';
tmp4 <= '0';
elsif (falling_edge(clk)) then
tmp1 <= drdy;
tmp2 <= tmp1;
tmp3 <= sclk;
tmp4 <= tmp3;
end if;
end process;
process (reset, clk)
begin
if (reset = '0') then
actual_state <= init;
elsif (rising_edge(clk)) then
actual_state <= next_state;
end if;
end process;
process (rise_sclk, rise_drdy) -- Next State affectation
begin
case actual_state is
when init =>
next_state <= wait_drdy;
ipdata <= (others => '0');
ipdready <= '0';
cnt <= (others => '0');
when wait_drdy =>
if (rise_drdy = '0') then
next_state <= actual_state;
else
next_state <= wait_sclk;
end if;
cnt <= (others => '0');
when wait_sclk =>
if (rise_sclk = '0') then
next_state <= actual_state;
else
next_state <= inc_count;
end if;
ipdready <= '0';
when inc_count =>
next_state <= check_count;
cnt <= cnt + 1;
ipdready <= '0';
ipdata(23 downto 1) <= ipdata(22 downto 0);
ipdata(0) <= sdata;
when check_count =>
case cnt is
when "11000" =>
next_state <= wait_drdy;
ipdready <= '1';
when others =>
next_state <= wait_sclk;
ipdready <= '0';
end case;
when others =>
next_state <= init;
end case;
end process;
end Behavioral;
My problem is during the check_count state ...
I'm expecting that this state should last one system clock cycle, but actually it last much more.
Here a snapshot of the behavioral simulation:
Due to the fact that this state last more than expected, i miss the following SCLK pulse and don't record the next bit ...
I don't understand why this state last so many system clock cycles instead of just one ...
Anyone has some clues and bring some light in my dark night ?
Thanks in advance.
Edit: I've tried to change the signal cnt for an integer variable internal to the process of the FSM ... Same results
The error is this:
process (rise_sclk, rise_drdy) -- Next State affectation
begin
-- code omitted, but does generally this:
next_state <= SOME_VALUE;
end process;
Because the sensitivity list includes only the signals rise_sclk and rise_drdy, the process is "executed" only if any of these signals changes. You can follow this in the wave diagram.
You don't have a synchronous design running on clk. Put clk on the sensitivity list and base the decisions on the levels of rise_sclk and rise_drdy. As an excerpt:
process (clk) -- Next State affectation
begin
if rising_edge(clk) then
case actual_state is
when init =>
next_state <= wait_drdy;
-- and so on
end case;
end if;
end process;
I have a structured implementation of 10-bit multiplier in which their is one control unit which keeps the track of the states and updates accordingly. Their is a counter named temp_count which should update and tell me whether I have completed the task or not. I wish I could attach the picture of simulation but I can't access it. I will update it later. Here's the code if someone could help me.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity Controller is
port (reset : in std_logic ;
clk : in std_logic ;
START : in std_logic ;
LSB : in std_logic ;
ADD_cmd : out std_logic ;
SHIFT_cmd : out std_logic ;
LOAD_cmd : out std_logic ;
STOP : out std_logic);
end;
architecture rtl of Controller is
signal temp_count : std_logic_vector(3 downto 0);
-- declare states
type state_typ is (IDLE, INIT, TEST, ADD, SHIFT);
signal state : state_typ;
begin
process (clk, reset)
begin
if reset='0' then
state <= IDLE;
temp_count <= "0000";
elsif (clk'event and clk='1') then
when IDLE =>
if START = '1' then
state <= INIT;
else
state <= IDLE;
end if;
when INIT =>
state <= TEST;
when TEST =>
if LSB = '0' then
state <= SHIFT;
else
state <= ADD;
end if;
when ADD =>
state <= SHIFT;
when SHIFT =>
if temp_count = "1001" then -- verify if finished
temp_count <= "0000"; -- re-initialize counter
state <= IDLE; -- ready for next multiply
else
temp_count <= temp_count + 1; -- increment counter
state <= TEST;
end if;
end case;
end if;
end process;
STOP <= '1' when state = IDLE else '0';
ADD_cmd <= '1' when state = ADD else '0';
SHIFT_cmd <= '1' when state = SHIFT else '0';
LOAD_cmd <= '1' when state = INIT else '0';
end rtl;
My VHDL-Code is functionaly correct, in ModelSim every thing works fine. I tested it with many variations and the code is functionaly correct.
But when I put it on the Altera board it displays a "3" on the 7-segment display, but it should show "0".
If I put RESET to "1" it breaks completly and displays only a line in the top segment.
My Inputs X, CLK, RESET are connected to the switches.
LOAD ist connected to a button and DIGIT to the 7-segment display.
It should have a clock signal as I swtich the CLK-switch.
Here my full code:
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
ENTITY seqdec IS
PORT ( X: IN std_logic_vector(15 DOWNTO 0);
CLK: IN std_logic;
RESET: IN std_logic;
LOAD: IN std_logic;
DIGIT: OUT std_logic_vector(6 DOWNTO 0) := "1111110";
Y: OUT std_logic);
END seqdec;
ARCHITECTURE SEQ OF seqdec IS
TYPE statetype IS (s0, s1, s2, s3, s4);
SIGNAL state: statetype:=s0;
SIGNAL next_state: statetype;
SIGNAL counter: std_logic_vector(2 DOWNTO 0) :="000" ;
SIGNAL temp: std_logic_vector(15 DOWNTO 0):= (OTHERS => '0');
SIGNAL so: std_logic := 'U';
-------------------Aktualisierung des Zustandes--------------------------------
BEGIN
STATE_AKT: PROCESS (CLK, RESET)
BEGIN
IF RESET = '1' THEN
state <= s0;
ELSIF CLK = '1' AND CLK'event THEN
state <= next_state ;
END IF;
END PROCESS STATE_AKT;
---------------------Counter---------------------------------------------------
COUNT: PROCESS (state, RESET)
BEGIN
IF (RESET = '1') THEN
counter <= (OTHERS => '0');
ELSIF (state = s4) THEN
counter <= counter + '1';
END IF;
END PROCESS COUNT;
-------------------PiSo für die Eingabe des zu Prüfenden Vektors---------------
PISO: PROCESS (CLK, LOAD, X)
BEGIN
IF (LOAD = '1') THEN
temp(15 DOWNTO 0) <= X(15 DOWNTO 0);
ELSIF (CLK'event and CLK='1') THEN
so <= temp(15);
temp(15 DOWNTO 1) <= temp(14 DOWNTO 0);
temp(0) <= '0';
END IF;
END PROCESS PISO;
-------------------Zustandsabfrage und Berechnung------------------------------
STATE_CAL: PROCESS (so,state)
BEGIN
next_state <= state;
Y <= '0';
CASE state IS
WHEN s0 =>
IF so = '1' THEN
next_state <= s0 ;
END IF;
WHEN s1 =>
IF so = '1' THEN
next_state <= s1;
END IF;
WHEN s2 =>
IF so = '0' THEN
next_state <= s3 ;
END IF;
WHEN s3 =>
IF so = '0' THEN
next_state <= s0 ;
ELSE
next_state <= s4 ;
END IF;
WHEN s4 =>
Y <= '1';
IF so = '0' THEN
next_state <= s0;
ELSE
next_state <= s2 ;
END IF;
WHEN OTHERS => NULL;
END CASE;
END PROCESS STATE_CAL;
-------------------7 Segment---------------------------------------------------
SEVEN_SEG: PROCESS (counter)
BEGIN
CASE counter IS
WHEN "000" => DIGIT <= "1111110";
WHEN "001" => DIGIT <= "0110000";
WHEN "010" => DIGIT <= "1101101";
WHEN "011" => DIGIT <= "1111001";
WHEN "100" => DIGIT <= "0110011";
WHEN "101" => DIGIT <= "1011011";
WHEN OTHERS => NULL;
END CASE;
END PROCESS SEVEN_SEG;
END SEQ;
I am pretty new to VHDL and am pretty sure it hase to do something with the timings, cause the functional part should be fine, as already said.
Hope for some hints, tips or even solutions.
EDIT: new code without LOAD, is this a valid idea? (non the less the whole code is not working on the FPGA....)
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
ENTITY seqdec IS
PORT ( X: IN std_logic_vector(15 DOWNTO 0);
CLK: IN std_logic;
RESET: IN std_logic;
LOAD: IN std_logic;
DIGIT: OUT std_logic_vector(0 TO 6) := "0000001";
Y: OUT std_logic);
END seqdec;
ARCHITECTURE SEQ OF seqdec IS
TYPE statetype IS (s0, s1, s2, s3, s4);
SIGNAL state: statetype:=s0;
SIGNAL next_state: statetype;
SIGNAL counter: std_logic_vector(2 DOWNTO 0) :="000" ;
SIGNAL temp: std_logic_vector(15 DOWNTO 0):= (OTHERS => '0');
SIGNAL so: std_logic := 'U';
-------------------Aktualisierung des Zustandes--------------------------------
BEGIN
STATE_AKT: PROCESS (CLK, RESET)
BEGIN
IF RESET = '1' THEN
state <= s0;
ELSIF CLK = '1' AND CLK'event THEN
state <= next_state ;
END IF;
END PROCESS STATE_AKT;
---------------------Counter---------------------------------------------------
COUNT: PROCESS (state, RESET)
BEGIN
IF (RESET = '1') THEN
counter <= (OTHERS => '0');
ELSIF (state = s4) THEN
counter <= counter + '1';
END IF;
END PROCESS COUNT;
-------------------PiSo für die Eingabe des zu Prüfenden Vektors---------------
PISO: PROCESS (CLK, LOAD, X)
BEGIN
IF (CLK'event and CLK='1') THEN
IF (LOAD = '1') THEN
temp(15 DOWNTO 0) <= X(15 DOWNTO 0);
ELSE
so <= temp(15);
temp(15 DOWNTO 1) <= temp(14 DOWNTO 0);
temp(0) <= '0';
END IF;
END IF;
END PROCESS PISO;
-------------------Zustandsabfrage und Berechnung------------------------------
STATE_CAL: PROCESS (so,state)
BEGIN
next_state <= state;
Y <= '0';
CASE state IS
WHEN s0 =>
IF so = '1' THEN
next_state <= s1 ;
END IF;
WHEN s1 =>
IF so = '1' THEN
next_state <= s2;
END IF;
WHEN s2 =>
IF so = '0' THEN
next_state <= s3 ;
END IF;
WHEN s3 =>
IF so = '0' THEN
next_state <= s0 ;
ELSE
next_state <= s4 ;
END IF;
WHEN s4 =>
Y <= '1';
IF so = '0' THEN
next_state <= s0;
ELSE
next_state <= s2 ;
END IF;
WHEN OTHERS => NULL;
END CASE;
END PROCESS STATE_CAL;
-------------------7 Segment---------------------------------------------------
SEVEN_SEG: PROCESS (counter)
BEGIN
CASE counter IS
WHEN "000" => DIGIT <= "0000001";
WHEN "001" => DIGIT <= "1001111";
WHEN "010" => DIGIT <= "0010010";
WHEN "011" => DIGIT <= "0000110";
WHEN "100" => DIGIT <= "1001100";
WHEN "101" => DIGIT <= "0100100";
WHEN OTHERS => DIGIT <= "0000001";
END CASE;
END PROCESS SEVEN_SEG;
END SEQ;
EDIT: This is now my version.
It will still show a "0" no matter what I do.
I would assume it has to do with the COUNT and counter.
should i realize this as synchronous too?
Is the numeric and unsigned really that big of a problem? We did it that way at university.
And will it work when i put LOAD onto a slide switch???
Best regards
Adrian
Your code has several problems. Btw. a running simulation does not mean your design is correct, because you can simulate actions which can not be implemented in hardware.
Here is a list of problems:
You can not use a switch button as a clock signal. Buttons are no clock source! Either you implement a signal cleanup circuit (at least a debounce circuit, which requires another clock) or you use you clk signal as an enable.
Moreover, each of your signals needs a debounce circuit if connected to external switch buttons or toggle buttons unless your test board has debounced buttons...
Your state machine has an init state (that's OK), but you must assign the state to state instead of next_state.
Your code uses std_logic_unsigned, which is obsolete. You should use numeric_std and the type unsigned for your counter signal.
Your code intoduces an additional register for COUT is this intended?
Your PISO process uses an asynchronous LOAD signal this is not supported in hardware (assuming an FPGA as target device).
Depending on your synthesis tool it's possible that it will not recognize a FSM because your case statement does not fit the pattern for FSMs.
Seeing a fixed output pattern can be causes by an FSM fault. If your synthesizer recognizes a FSM, you can go to the state diagram and identify false edges or false terminal states.
More ...
Your 7-segment decoder is a combinatorical process. It can not be reset.
Moreover, this process is not sensitive to CLK, just to counter. This cause a mismatch between simulation and hardware. (Synthesis ignores sensitivity lists)
If you fix this, your simulation should have another behavior and, if fixed, work as your hardware :).
The FSM
STATE_CAL : process(state, so)
begin
-- Standardzuweisungen
next_state <= state; -- Bleib im Zustand falls in CASE nichts abweichendes bestimmt wird
Y <= '0';
-- Zustandswechsel
CASE state IS
WHEN s0 =>
IF (so = '1' THEN
next_state <= s1;
END IF;
WHEN s1 =>
IF (so = '1') THEN
next_state <= s2;
END IF;
WHEN s2 =>
IF (so = '0') THEN
next_state <= s3;
END IF;
WHEN s3 =>
IF (so = '0') THEN
next_state <= s0;
else
next_state <= s4;
END IF;
WHEN s4 =>
Y <= '1'; -- Moore-Ausgabe
IF (so = '0') THEN
next_state <= s0;
else
next_state <= s2;
END IF;
END CASE;
END PROCESS;
Paebbels already described many issues of your code. Please check also the warnings of your synthesis tool. They often indicate where the synthesizer actually outputs different logic than you have described in VHDL.
I suspect you have made another two mistakes which are not directly related to VHDL:
Your 7-segment display control lines seem to be low-active because you see only one active segment when you press RESET. This matches the only zero in the vector "1111110" you assigned in this case (via reseting counter to "000").
But even in this case, the enlighted segment should be in the middle instead on the top. Thus, your pin assignments seem to be in the reverse order.
How to set a bit on rising edge and reset that bit on falling edge of a clock signal?
I would like to know how i can achieve the same. Depending upon a condition i want to set on rising edge and reset on falling edge. It's like getting clock pulse itself at the output.
I implemented for two different clock pulses but i am getting glitches like these.
My code for same is as this
process(clk)
begin
if rising_edge(clk) then
d0 <= new_data;
end if;
end process;
process(clk)
begin
if falling_edge(clk) then
d1 <= new_data;
end if;
end process;
out <= d0 when clk = '1' else d1;
If you want DDR data, which is the only time I can see that you'd actually want to do this, there are a number of ways of modelling it. If you want synthesis, instantiate the appropriate vendors primitive
However, for a model:
process(clk)
begin
-- you could use this
if clock'event = '1' then
bit <= new_data;
end if;
-- or this
if rising_edge(clk) ot falling_edge(clk) then
bit <= new_data;
end if;
end process;
You could also model it as 2 processes and a mux
process(clk)
begin
if rising_edge(clk) then
d0 <= new_data;
end if;
end process;
process(clk)
begin
if falling_edge(clk) then
d1 <= new_data;
end if;
end process;
out <= d0 when clk = '1' else d1;
Having now seen your waveform, you could do the following to get a glitch free pulse train
process(clk)
begin
if falling_edge(clk) then
if pass_next_clock = '1' then
mask <= '1';
else
mask <= '0';
end if;
end if;
end process;
pulse <= clk and mask;
This requires you to have a signal called pass_next_clock, which can be aligned to either clock edge to signal that you want the next clock high pulse to be output.
Ok i got it work. My final code looks like
shared variables d0 ,d1 : std_logic;
process(clk)
begin
if rising_edge(clk) then
d0 := new_data;
end if;
end process;
process(clk)
begin
if falling_edge(clk) then
d1 := new_data;
end if;
end process;
out <= d0 when clk = '1' else d1;
I am trying to implement clock synchronization and clock divider in the following piece of VHDL code. The clocks(clk_rx and clk_tx) should synchronize at the rising and falling edges of 'RX' signal on the bus. I can simulate the following but it is not synthesizable in ISE since i am using " RX'EVENT ". Could any one suggest an alternative for this? (Verilog also will work)
-------------------------------------------- CLOCK DIVIDER----------------------------------------------------------------------------------------
PROCESS (CLK_I, RX)
BEGIN
IF (RX'EVENT) THEN
clk_cnt <= to_unsigned(0,clk_cnt'LENGTH);
ELSIF (CLK_I'EVENT AND CLK_I = '1') THEN
IF clk_cnt >2499 THEN
clk_cnt <= to_unsigned(0,clk_cnt'LENGTH);
ELSE
clk_cnt <= clk_cnt + 1;
END IF;
END IF;
END PROCESS;
clk_rx <= '1' WHEN clk_cnt = 1250 ELSE '0'; -----clk_rx=1 only at the half of the counter period----------clk enable
clk_tx <= '1' WHEN clk_cnt = 2499 ELSE '0';
You can find a suggestion for code below. Note the following properties:
clk_rx_o (clk_rx) and clk_rx_o (clk_tx) are generated as outputs from flip-flops, since to avoid glitches which may occur if the signals are generated based on combinatorial compare of cnt outside the process
rx_i is synchronized by two flip-flops, assuming that it is not already synchronous to clk_i
Clock division is by 2501, since cnt goes from 0 .. 2500 due to wrap when (cnt > 2499). For division by 2500 use (cnt >= 2499) instead.
VHDL coding style: All signal names are lower case, as are VHDL statements, consistent spacing around expressions for readability
Code:
library ieee;
use ieee.std_logic_1164.all;
entity mdl is
port(
clk_i : in std_logic;
rx_i : in std_logic;
clk_rx_o : out std_logic;
clk_tx_o : out std_logic);
end entity;
library ieee;
use ieee.numeric_std.all;
architecture syn of mdl is
signal rx_meta : std_logic;
signal rx_sync : std_logic;
signal cnt : std_logic_vector(12 - 1 downto 0);
begin
-- rx_i sync to clk_i
process (clk_i) is
begin
if rising_edge(clk_i) then
rx_meta <= rx_i;
rx_sync <= rx_meta;
end if;
end process;
process (clk_i) is
begin
if rising_edge(clk_i) then
-- Clock align and divide
if rx_sync = '1' then
cnt <= std_logic_vector(to_unsigned(0, cnt'length));
else
if unsigned(cnt) > 2499 then
cnt <= std_logic_vector(to_unsigned(0, cnt'length));
else
cnt <= std_logic_vector(unsigned(cnt) + 1);
end if;
end if;
-- Clock generate as single cycle pulse
clk_rx_o <= '0';
if unsigned(cnt) = 1250 then
clk_rx_o <= '1';
end if;
clk_tx_o <= '0';
if unsigned(cnt) = 2499 then
clk_tx_o <= '1';
end if;
end if;
end process;
end architecture;
The problem is not simply that you are using RX'EVENT, it's that you have a CLK_I'EVENT conditional inside an RX'EVENT condition. That's just not synthesizable.
Assuming that CLK_I is much higher frequency than RX'EVENT, try sampling RX using CLK_I. If the previous value of RX is low and the current value is high, then synchronously reset clk_cnt on CLK_I'EVENT. Note that if RX is truly asynchronous to CLK_I you need to worry about metastability and you should add 2 flip-flops to synchronize RX before you look for a change from 0 to 1.
Try this code. There are still no flip flops in my code to solve metastability of RX as #Joe Hass explains.
But there is a scheme for synchronizing the RX signal.
PROCESS (CLK_I, RX)
BEGIN
IF (CLK_I'EVENT AND CLK_I = '1') THEN
IF (RX='1') THEN
clk_cnt <= to_unsigned(0,clk_cnt'LENGTH);
ELSE
IF clk_cnt >2499 THEN
clk_cnt <= to_unsigned(0,clk_cnt'LENGTH);
ELSE
clk_cnt <= clk_cnt + 1;
END IF;
END IF;
END IF;
END PROCESS;
Thank you very much for your support.
I modified the code as #Joe and #MortenZdk suggested. Now I am able to synthesize it.
I have to detect both posedge and negedge of "RX". So I changed the code as follows:
PROCESS(CLK_I) -- Stabilizing the RX signal to avoid meta stable state
begin
if rising_edge(CLK_I) then
rx_meta <= RX;
rx_sync <= rx_meta;
end if;
END PROCESS;
PROCESS (CLK_I)
BEGIN
IF (CLK_I'EVENT AND CLK_I = '1') THEN
tmp_RX <= rx_sync;
IF (rx_sync /= tmp_RX) THEN
clk_cnt <= to_unsigned(0,clk_cnt'LENGTH);
ELSE
IF clk_cnt >2499 THEN
clk_cnt <= to_unsigned(0,clk_cnt'LENGTH);
ELSE
clk_cnt <= clk_cnt + 1;
END IF;
END IF;
-- Clock generate as single cycle pulse
clk_rx <= '0';
IF clk_cnt = 1250 THEN
clk_rx <= '1';
END IF;
clk_tx <= '0';
IF clk_cnt = 2500 THEN
clk_tx <= '1';
END IF;
END IF;
END PROCESS;