I need to run makefile again. but whenever I run 'make' I get 'skfit.2atoms.1kind' is up to date. I also tried .phony: clean. but It's not working. Can some one tell me exactly what command line I should add to overcome this problem?
here is my makefile.
CFT=gfortran
LDR=gfortran
COMMAND=skfit.2atoms.1kind
PROFLIB=
.SUFFIXES: .o .f
.f.o :
$(CFT) $(FFLAGS) -o $# -c $<
OBJS= skgen.o zxssq.o ludec.o luelm.o uertt.o \
func.o diag.o myhtdi.o myred.o mytql2.o fermi4sk.o hsort.o \
tnewef.o matri.o setup.o rotate.o quadroot.o symmeg.o \
input.o input1.o mapk.o multatoms.o search2.o shifttrue.o
$(COMMAND): $(OBJS)
$(LDR) $(LDFLAGS) -o $(COMMAND) $(OBJS) $(LIBS)
diag.o: P1
fermi4sk.o: P1
func.o: P1 P2 P3
input.o: P1
input1.o: P1
matri.o: P1
multatoms.o: P1
rotate.o: P1
search2.o: P1
setup.o: P1
shifttrue.o: P1 P2
skgen.o: P1 P2 P3
symmeg.o: P1 P2
Related
My makefile currently looks like this:
#Source file locations
VPATH = :../AHMCodePara
#Compiler
CC = mpifort
#Debugging Flags
#Flags =
#Regular flags
Flags = -Ofast -mkl=sequential
# File name labels
FF =
DE =
Const =
OBJDIR = OBJ
# make object directory
$(OBJDIR):
-mkdir $(OBJDIR)
CC += -module $(OBJDIR)
#Object File List
Inputs =
Tools = $(OBJDIR)/$(Const)Inputs.o
Diag$(DE) = $(Tools)
PreAnalysis = $(Tools) $(OBJDIR)/Tools.o
DOSsetupPara$(DE) = $(PreAnalysis) $(OBJDIR)/PreAnalysis.o $(OBJDIR)/Diag$(DE).o
$(Const)AHMRGv3 = $(Tools) $(OBJDIR)/Diag$(DE).o $(OBJDIR)/DOSsetupPARA$(DE).o
#Object File List
obj = $(OBJDIR)/$(Const)Inputs.o $(OBJDIR)/Diag$(DE).o $(OBJDIR)/Tools.o \
$(OBJDIR)/PreAnalysis.o $(OBJDIR)/DOSsetupPARA$(DE).o $(OBJDIR)/$(Const)AHMRGv3.o
# dependence files
$(OBJDIR)/%.o: %.f90 $(%)
# #$(%)
#-rm -f #<~
$(CC) -c $< -o $# $(Flags)
All: V3.e
# Target
V3.e: $(obj)
$(CC) $(Flags) -o $# $^
clean:
rm $(OBJDIR)/*.o $(OBJDIR)/*.mod
It used to be similar to this one:
LOC = ../../AHMCode/
CC = gfortran
#Debugging
#Flags = -O0 -g -fcheck=all -Wall -llapack
#Normal
Flags = -O3 -I/usr/lib/ -L/usr/lib/ -lblas -llapack
FF = _Old
IG = #IGNORE or nothing
TT = #TYPE or nothing
V3$(FF).e: Inputs.o Tools.o PreAnalysis.o DOSsetup$(IG).o Diag$(TT).o AHMRGv3_Manyruns.o
$(CC) $(Flags) AHMRGv3_Manyruns.o Diag$(TT).o DOSsetup$(IG).o PreAnalysis.o Tools.o Inputs.o -o V3$(FF).e
Inputs.o: Inputs.f90
$(CC) $(Flags) -c Inputs.f90
Tools.o: $(LOC)Tools.f90 Inputs.o
$(CC) $(Flags) -c $(LOC)Tools.f90
PreAnalysis.o: $(LOC)PreAnalysis.f90 Inputs.o Tools.o
$(CC) $(Flags) -c $(LOC)PreAnalysis.f90
DOSsetup$(IG).o: $(LOC)DOSsetup$(IG).f90 Inputs.o Tools.o PreAnalysis.o Diag$(TT).o
$(CC) $(Flags) -c $(LOC)DOSsetup$(IG).f90
Diag$(TT).o: $(LOC)Diag$(TT).f90 Inputs.o
$(CC) $(Flags) -c $(LOC)Diag$(TT).f90
AHMRGv3_Manyruns.o: AHMRGv3_ManyRuns.f90 DOSsetup$(IG).o Diag$(TT).o Inputs.o
$(CC) $(Flags) -c AHMRGv3_Manyruns.f90
clean:
rm *.o *.mod
The section I want to compare in these makefiles is the .o file definitions. In the second makefile, I wrote these all out by hand and it worked great. My intention with the second makefile was to do the same thing but more efficiently.
The problems arose with dependencies. When I initially made changes to my makefile, I didn't put any dependencies at all. This led to problems where I would update Inputs and the relevant files wouldn't recompile (e.g. Tools.o). This is as expected so I've been looking for ways to add dependencies in a creative and efficient way that forces the relevant files to recompile.
As you can see I tried creating variables with the same name as the .f90 and .o to use $(%). This seemed kinda janky (and I didn't really think it would work) but unfortunately didn't solve my problem.
As you can see from the original makefile, the dependencies don't follow any sort of pattern. As well you can see that I am compiling Fortran and I'm pretty sure that -gen-dep doesn't do anything and if it does I'm doing it wrong.
Existing questions on the subject have been very unhelpful since the majority uses C++ and that can be very different here.
EDIT: I "fixed" my problem. Its not the most efficient and doesn't automatically generate dependencies but I like it in that its not a lot of repetitive lines.
#Object File List
oInpt =
oTool = $(OBJDIR)/$(Const)Inputs.o
oPreA = $(oTool) $(OBJDIR)/Tools.o
oDOSs = $(oPreA) $(OBJDIR)/PreAnalysis.o $(OBJDIR)/Diag$(DE).o
oDiag = $(oTool)
oMain = $(oTool) $(OBJDIR)/Diag$(DE).o $(OBJDIR)/DOSsetupPARA$(DE).o
obj = $(OBJDIR)/$(Const)Inputs.o $(OBJDIR)/Tools.o $(OBJDIR)/PreAnalysis.o $(OBJDIR)/Diag$(DE).o \
$(OBJDIR)/DOSsetupPARA$(DE).o $(OBJDIR)/$(Const)AHMRGv3.o
# dependence files
$(OBJDIR)/$(Const)Inputs.o: $(oInpt)
$(OBJDIR)/Tools.o: $(oTool)
$(OBJDIR)/PreAnalysis.o: $(oPreA)
$(OBJDIR)/Diag$(DE).o: $(oDiag)
$(OBJDIR)/DOSsetupPARA$(DE).o: $(oDOSs)
$(OBJDIR)/$(Const)AHMRGv3.o: $(oMain)
$(OBJDIR)/%.o: %.f90
#-rm -f #<~
$(CC) -c $< -o $# $(Flags)
All: V3.e
# Target
V3.e: $(obj)
$(CC) $(Flags) -o $# $^
I just made multiple rules for each target. One a default rule that actually compiles the .o files and the other that specifies the dependencies for each .f90 file.
I'm trying to get my Makefile to compile only changed source files. In the Makefile below, I would like the targets: %.o : ${SOURCE_DIR}/%.c and %.o : ${SOURCE_DIR}/%.s to only compile if the source file has changed, or the corresponding .o object file does not exist.
Not entirely sure what's wrong here, can someone please offer some advice?
# Project name
# ---------------------------------------------------------------------------------------------------------------------
PROJECT_NAME = stm32f4_template
# Source configuration
# ---------------------------------------------------------------------------------------------------------------------
OUT_DIR = ./Build
SOURCE_DIR = ./Src
SOURCES = main.c
SOURCES += startup.s
C_SOURCES = $(filter %.c, $(SOURCES))
ASM_SOURCES += $(filter %.s, $(SOURCES))
OBJECTS = $(C_SOURCES:.c=.o)
OBJECTS += $(ASM_SOURCES:.s=.o)
# Tools
# ---------------------------------------------------------------------------------------------------------------------
CC = arm-none-eabi-gcc
LD = arm-none-eabi-ld -v
CP = arm-none-eabi-objcopy
OD = arm-none-eabi-objdump
# Compilation, linker and other tool flags
# ---------------------------------------------------------------------------------------------------------------------
CFLAGS = -I./ -c -fno-common -O0 -g -mcpu=cortex-m4 -mthumb
LFLAGS = -nostartfiles -TLinker/memory.ld -TLinker/sections.ld
CPFLAGS = -Obinary
ODFLAGS = -S
# Target: all ---------------------------------------------------------------------------------------------------------
#
all: setup $(PROJECT_NAME).elf
#echo "Done! $?"
# Target: setup -------------------------------------------------------------------------------------------------------
#
setup:
#mkdir -p $(OUT_DIR)
# Target: $(PROJECT_NAME).elf
# ---------------------------------------------------------------------------------------------------------------------
$(PROJECT_NAME).elf: $(OBJECTS)
#echo "Linking $#"
$(LD) $(LFLAGS) -o ${OUT_DIR}/main.elf $(OUT_DIR)/main.o
#echo
# Target %.o (.c sources)
# ---------------------------------------------------------------------------------------------------------------------
%.o : ${SOURCE_DIR}/%.c # --> Execute only if source changed!!!
#echo "Compiling $<"
$(CC) $(CFLAGS) $< -o $(OUT_DIR)/$#
#echo
# Target %.o (.s sources)
# ---------------------------------------------------------------------------------------------------------------------
%.o : ${SOURCE_DIR}/%.s # --> Execute only if source changed!!!
#echo "Compiling $<"
$(CC) $(CFLAGS) $< -o $(OUT_DIR)/$#
#echo
# Target: clean
# ---------------------------------------------------------------------------------------------------------------------
clean:
#echo "Cleaning build output..."
#rm -rf $(OUT_DIR)
This rule:
%.o : ${SOURCE_DIR}/%.c # --> Execute only if source changed!!!
#echo "Compiling $<"
$(CC) $(CFLAGS) $< -o $(OUT_DIR)/$#
The problem is that the target of this rule is main.o, so Make uses it in an attempt to build main.o, because another target demands main.o, but what this rule actually builds is Build/main.o. Make keeps running this rule because it sees that main.o isn't there (and the rule for the elf file uses Build/main.o, which Make keeps rebuilding unawares).
I suggest you change it:
OBJECTS = $(patsubst %.c, $(OUT_DIR)/%.o, $(C_SOURCES))
$(OUT_DIR)/%.o : ${SOURCE_DIR}/%.c # --> this should work
#echo "Compiling $<"
$(CC) $(CFLAGS) $< -o $#
The same goes for the other %.o rule.
In trying to implement nonrecursive make, I have a Rules.mk which looks like:
############
# Enter Stack
############
sp := $(sp).x
dirstack_$(sp) := $(d)
d := $(dir)
.. setup things like OBJECTS_$(d), DEPS_$(d), TARGET_$(d), etc ...
############
# Exit Stack
############
-include $(DEPS_$(d))
d := $(dirstack_$(sp))
sp := $(basename $(sp))
One of the variables I wanted to set was:
INCLUDE_PATH_$(d) := -Isomething -Isomething/else ...
To be used in the compilation rule:
$(OBJDIR_$(d))/%.o : $(d)/%.cpp $(OBJDIR_$(d))/%.d
$(CC) $(CFLAGS) $(INCLUDE_PATH_$(d)) -o $# -c $<
But this doesn't work - $(INCLUDE_PATH_$(d)) doesn't get expanded until later - when $(d) is no longer has the value I need it to have in order for this to work. What's the way for me to do this properly?
You could use a target-specific variable
$(OBJDIR_$d)/%.o : INCLUDES := $(INCLUDE_PATH_$d)
$(OBJDIR_$d)/%.o : $d/%.cpp $(OBJDIR_$d)/%.d
$(CC) $(CFLAGS) $(INCLUDES) -o $# -c $<
The following is perhaps more standard / flexible (assuming CPPFLAGS isn't set to recursively expand) although it depends on your needs
$(OBJDIR_$d)/%.o : CPPFLAGS += $(INCLUDE_PATH_$d)
$(OBJDIR_$d)/%.o : $d/%.cpp $(OBJDIR_$d)/%.d
$(CC) $(CPPFLAGS) $(CFLAGS) -o $# -c $<
Somewhere I am going wrong !!
I am trying to generate the object files in ../bin/
But the below code generates in corresponding source file directory.
Below the code, which I am running.
Modified code:
LIB = $(BIN_DIR)/libutils.a
APP = $(BIN_DIR)/app
CC = gcc
AR = ar
CFLAGS = -Wall -g
LDFLAGS =
all: $(LIB) $(APP)
SRC = $(SRC_DIR)/add.c \
$(SRC_DIR)/sub.c
OBJ = $(SRC:.c=.o)
INCLUDES = -I$(INC_DIR)/
LIBS = -L../ -L/usr/local/lib -lm
LDFLAGS = -g
.SUFFIXES: .c
.c.o:
$(CC) $(INCLUDES) -c $(SRC_DIR)/$< -o $(BIN_DIR)/$#
$(LIB): $(OBJ)
$(AR) rcs $(LIB) $(OBJ)
$(BIN_DIR)/app: $(BIN_DIR)/test.o \
$(BIN_DIR)/t.o \
$(BIN_DIR)/libutils.a
$(CC) $(LDFLAGS) -o $# $^
clean:
rm -f $(LIB) $(BIN_DIR)/* $(SRC_DIR)/*.o *.o
Thank you :)
You still have the rule:
$(LIB): $(OBJ)
...
and OBJ is still src_dir/add.o src_dir/sub.o, so that's where Make will try to build these objects if your object rule works as intended. So, first step:
SRC = $(SRC_DIR)/add.c \
$(SRC_DIR)/sub.c
OBJ = $(SRC:.c=.o)
OBJ = $(patsubst $(SRC_DIR)/%.c,$(BIN_DIR)/%.o,$(SRC))
Now you'll find that your object rule,
.c.o:
...
doesn't work, because it expects to find the source file in the same place where the object file should go (i.e. $(OBJ_DIR)). So replace this rule with:
$(BIN_DIR)/%.o: $(SRC_DIR)/%.c
$(CC) $(INCLUDES) -c $< -o $#
I notice that you have no provision for building $(BIN_DIR)/t.o and $(BIN_DIR)/test.o, but the app needs them. You should look into that.
Further refinements are possible, but this is a start.
Your SRC has a relative path, and your OBJ is just the SRC with the extension changed to. o
So OBJ will contain this:
../src/add.o
../src/sub.o
And there is where the .o will be created.
Make these changes and it will work:
SRC = add.c \
sub.c
.c.o:
$(CC) $(INCLUDES) -c ../src/$< -o ../bin/$#
In continuation with my earlier question
Makefile - compiling back and forth
I made an attempt in creating a single Makefile. The two subdirectories are HAM-src and GFS-src. However, I am still unable to build it. I paste my Makefile below:
export
SHELL = /bin/sh
top_srcdir=./Temp
objdir=$(top_srcdir)/obj
bindir=${exec_prefix}/bin
cfssrcdir=${top_srcdir}/GFS-src
hamsrcdir=${top_srcdir}/HAM-src
incdir=${top_srcdir}/include
exec=${bindir}/esm_gfs-ham_v0
PROG=$(exec)
LDR = mpxlf90_r -qsmp=noauto
FFLAG90 = $(OPTS90) $(FINCS) -qfree=f90 -NS2048 -qmoddir=$(objdir) -I$(objdir)
FFLAGM = -NS2048 -qfixed -qmoddir=$(objdir) -I$(objdir)
F77 = mpxlf95
F90 = mpxlf95
F90_x = xlf90_r
F90_r = mpxlf95_r
SRCHAM = $(hamsrcdir)/ham_control.f90 $(hamsrcdir)/mo_filename.f90 \
$(hamsrcdir)/ham_namelist.f90 $(hamsrcdir)/ham_submodel.f90 \
$(hamsrcdir)/ham_submodel_diag.f90 $(hamsrcdir)/ham_ham.f90
SRCGFS_MOD=$(cfssrcdir)/machine.f $(cfssrcdir)/resol_def.f \
$(cfssrcdir)/omegas.f $(cfssrcdir)/cnvcld_v.f
OBJGFS_MOD = $(patsubst $(cfssrcdir)/%.f,$(objdir)/%.o,$(SRCGFS_MOD))
OBJHAM = $(patsubst $(hamsrcdir)/%.f90,$(objdir)/%.o,$(SRCHAM))
.SUFFIXES: $(SUFFIXES) .f90 .f .o
all: $(PROG)
$(PROG): $(OBJHAM) $(OBJGFS_MOD)
$(LDR) $(CFS_LDFLAGS) -o $# $(OBJGFS_MOD) $(OBJHAM) $(CFS_LIBS) -L$(LDFLAGS)
$(objdir)/%.o: $(cfssrcdir)/%.f
$(F77) $(FFLAGS) -c $< -o $#
$(objdir)/%.o: $(hamsrcdir)/%.f90
$(F90_r) $(F90FLAGS) -c $< -o $#
########## dependencies for $(hamsrcdir) ###########
ham_filename.o: ham_control.o
ham_namelist.o: ham_control.o ham_filename.o
ham_submodel.o: ham_control.o ham_namelist.o $(objdir)/resol_def.o
ham_submodel_diag.o: ham_submodel.o
########## dependencies for $(cfssrcdir) ###########
$(objdir)/omegas.o: $(cfssrcdir)/omegas.f
$(F77) $(FFLAGM) -c $(cfssrcdir)/omegas.f -o $#
$(objdir)/cnvcld_v.o: $(cfssrcdir)/cnvcld_v.f
$(F77) $(FFLAGM) -c $(cfssrcdir)/cnvcld_v.f -o $#
The error:
mpxlf95_r -q64 -O3 -qstrict -qMAXMEM=-1 -qarch=auto -qtune=auto -qcache=auto -qfloat=fltint -qsuffix=cpp=f90 -lessl_r -lmass -lmassv -I./Temp/include -I./Temp/HAM-src -qmoddir=./Temp/obj -I./Temp/obj -c ./Temp/HAM-src/ham_namelist.f90 -o ./Temp/obj/ham_namelist.o
** ham_namelist === End of Compilation 1 ===
1501-510 Compilation successful for file ham_namelist.f90.
mpxlf95_r -q64 -O3 -qstrict -qMAXMEM=-1 -qarch=auto -qtune=auto -qcache=auto -qfloat=fltint -qsuffix=cpp=f90 -lessl_r -lmass -lmassv -I./Temp/include -./Temp/HAM-src -qmoddir=./Temp/obj -I./Temp/obj -c ./Temp/HAM-src/ham_submodel.f90 -o ./Temp/obj/ham_submodel.o
"./Temp/HAM-src/ham_submodel.f90", line 425.7: 1514-219 (S) Unable to access module symbol file for module resol_def. Check path and file permissions of file. Use association not done for this module.
1501-511 Compilation failed for file ham_submodel.f90.
gmake: *** [/gpfs1/home/cccrmod/ham_expt_dec11/regrid_test/CFS-HAM/SORC_CFS-HAM/Temp/obj/ham_submodel.o] Error 1
Why makefile does not compile the resol_def.f module on encountering the dependency?
Another issue - my makefile is not working properly. It goes in a sequence in which the sources are defined.
This is difficult to untangle (a minimal, complete example really would help), but I'd suggest you change this
ham_submodel.o: ham_control.o ham_namelist.o $(objdir)/resol_def.o
to this
$(objdir)/ham_submodel.o: ham_control.o ham_namelist.o $(objdir)/resol_def.o
and see if that solves the first problem. I don't understand the last line of your question ("Another issue...").