I'm making this code, but I don't know how to deal with this warning.
The warnings are on the process site. In this specifically
process (boton) begin
if (boton= '1') Then
ienable <= '1';
else
brojo <= '0';
bamarillo <= '0';
bverde <= '1';
END IF;
END process;
-- University: Universidad Tecnica Nacional(UTN)
-- Course: Aplicaciones de FPGA
-- Developed by: Massiel Angulo Mejia
-- Module name: Semaforo_Top
-- Date: 08/11/2022
-- File name: Semaforo_Top.vhd
------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Semaforo is port (
CLK_100MHz, boton :in std_logic; -- Define las entradas de 1 bit
R, A, V :out std_logic); -- Define la salida de 1 bit
end Semaforo;
architecture Behavioral of Semaforo is
signal rojo, amarillo, verde, puente, aca :std_logic := '0';
signal brojo, bamarillo, bverde :std_logic := '0';
signal q0, q1, q2, q3, q4, q5, enable, ienable :std_logic := '0';
signal r1, r2, r3, r4, r5, r6, r7, r8, r9, r10 :std_logic := '0';
signal a1, a2, a3, a4, a5, btn :std_logic := '0';
signal v1, v2, v3, vr, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15 :std_logic := '0';
component Contador5bits port (
CLK_100MHz :in STD_LOGIC; -- Define la entrada de 1 bit
reset :in STD_LOGIC; -- Define la entrada de 1 bit
pausa :in STD_LOGIC; -- Define la entrada de 1 bit
en :in STD_LOGIC; -- Define la entrada de 1 bit
acarreo :out STD_LOGIC; -- Define la salida de 1 bit
salida :out STD_LOGIC_VECTOR(4 downto 0) :=(others => '0') -- Define la salida de 5 bits
);
end component;
component FrequencyDivider
generic(
M :integer; -- Factor parametrizable en la instanciacion
N :integer); -- Factor parametrizable en la instanciacion
PORT(
clk_in :in STD_LOGIC; -- Define las entradas de 1 bit
clk_out :out STD_LOGIC); -- Define la salida de 1 bit
end component; -- Termina la definicion del componente
begin
process (boton) begin
if (boton = '1') Then
ienable <= '1';
else
brojo <= '0';
bamarillo <= '0';
bverde <= '1';
END IF;
END process;
--Inicio del decodificador para led verde
v1 <= not(q4) and not(q3) and not(q2) and not(q1) and q0;
v2 <= not(q4) and not(q3) and not(q2) and q1 and not(q0);
v3 <= not(q4) and not(q3) and not(q2) and q1 and q0;
--Inicio del decodificador para led amarillo
a1 <= not(q4) and q3 and not(q2) and q1 and q0;
a2 <= not(q4) and q3 and q2 and not(q1) and not(q0);
a3 <= not(q4) and q3 and q2 and not(q1) and q0;
a4 <= not(q4) and q3 and q2 and q1 and not(q0);
a5 <= not(q4) and q3 and q2 and q1 and q0;
--Inicio del decodificadotr para led rojo
r1 <= q4 and not(q3) and not(q2) and not(q1) and not(q0);
r2 <= q4 and not(q3) and not(q2) and not(q1) and q0;
r3 <= q4 and not(q3) and not(q2) and q1 and not(q0);
r4 <= q4 and not(q3) and not(q2) and q1 and q0;
r5 <= q4 and not(q3) and q2 and not(q1) and not(q0);
r6 <= q4 and not(q3) and q2 and not(q1) and q0;
r7 <= q4 and not(q3) and q2 and q1 and not(q0);
r8 <= q4 and not(q3) and q2 and q1 and q0;
r9 <= q4 and q3 and not(q2) and not(q1) and not(q0);
r10 <= q4 and q3 and not(q2) and not(q1) and q0;
---Reinicio en verde
vr <= q4 and not(q3) and not(q2) and q1 and q0;
--Inicio de instancia de las salidas
rojo <= r1 or r2 or r3 or r4 or r5 or r6 or r7 or r8 or r9 or r10;
amarillo <= a1 or a2 or a3 or a4 or a5;
verde <= v1 or v2 or v3;
enable <= ienable;
--Instancia de las salidas
R <= rojo and brojo;
A <= amarillo and bamarillo;
V <= verde or bverde;
--Instancia del contador de 5 bits que cuenta 18s
Cnt5bits :Contador5bits port map(
CLK_100MHz => puente,
reset => '0',
pausa => '0',
en => enable,
acarreo => aca,
salida (0) => q0,
salida (1) => q1,
salida (2) => q2,
salida (3) => q3,
salida (4) => q4
);
-- Se realiza la instancia del componente
divisor_1Hz :FrequencyDivider generic map(M => 100_000_000, N => 27) port map( -- Paso de parametros (M,N) en la instancia
clk_in => CLK_100MHz,
clk_out => puente
); -- Final de la instancia
end Behavioral;```
The thing in that part is that when you press boton enable is 1 and when boton is 0 brojo, bamarillo are 0 and bverde is 1.
Help me editing the process block to delete that warnings.
When you synthesize a HDL code and you do not provide a sender to a signal at all time, you will always get a latch and a latch warning. In your case you do not provide a sender to brojo, bamarillo, bverde for the case when boton=1 and no sender to ienable for the case when boton=0. But in hardware there must exist a sender at any time, this is why a latch is inserted and provides the last assigned value to the undriven signal. In almost all cases latches inferred in this way are not wanted and bad design which will probably cause trouble later on in the design flow.
Related
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity sammy_2018314405 is
Port ( codeword : in STD_LOGIC_VECTOR (6 downto 0);
syndrome : out STD_LOGIC_VECTOR (2 downto 0);
dataword : out STD_LOGIC_VECTOR (3 downto 0));
end sammy_2018314405;
architecture Behavioral of sammy_2018314405 is
signal s : std_logic_vector(2 downto 0);
signal b3, b2, b1, b0, q2, q1, q0 : std_logic;
signal temp : std_logic_vector(6 downto 0);
begin
b3 <= codeword(6);
b2 <= codeword(5);
b1 <= codeword(4);
b0 <= codeword(3);
q2 <= codeword(2);
q1 <= codeword(1);
q0 <= codeword(0);
s(0) <= b0 xor b1 xor b2 xor q0;
s(1) <= b1 xor b2 xor b3 xor q1;
s(2) <= b0 xor b1 xor b3 xor q2;
temp <= (b3,b2,b1,b0,q2,q1,q0);
--this part show error, can I put case in the middle of the code?
process(s)
begin
case s is
when "001" => temp(0) <= not temp(0);
when "010" => temp(1) <= not temp(1);
when "011" => temp(5) <= not temp(5);
when "100" => temp(2) <= not temp(2);
when "101" => temp(3) <= not temp(3);
when "110" => temp(6) <= not temp(6);
when "111" => temp(4) <= not temp(4);
when others => null;
end case;
end process;
syndrome(2 downto 0) <= s(2 downto 0);
dataword(3 downto 0) <= temp(6 downto 3);
end Behavioral;
Line 51: Net <temp[6]> is already driven by input port <codeword[6]>.
Net <temp[5]> is already driven by input port <codeword[5]>.
(This is code for 7 4 Hamming decoder.)
What should I do?
I am trying write a 8 bit up counter from 0 to 99 then return to 0 , with jk flip flop in VHDL, with active hdl program. but its do nothing. where is the problem?
jk flip flop with asynchron reset :
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity JK is
port(
J, K, clk, clr : in std_logic;
Q, Qbar : out std_logic
);
end JK;
architecture arch of JK is
signal D : std_logic;
signal Dn : std_logic;
signal clkn : std_logic;
signal clrn : std_logic;
signal o1 : std_logic := '1';
signal o2 : std_logic := '0';
signal o3 : std_logic := '0';
signal o4 : std_logic := '1';
signal o5 : std_logic := '0';
signal o6 : std_logic := '1';
signal o7 : std_logic := '1';
signal o8 : std_logic := '0';
begin
D <= (o8 and (not K)) or (o7 and J);
Dn <= not D;
clkn <= not clk;
clrn <= not clr;
o1 <= Dn and clkn;
o2 <= D and clkn and clrn;
o3 <= not (o4 or o1 or clr);
o4 <= o3 nor o2;
o5 <= o3 and clk;
o6 <= o4 and clk;
o7 <= o8 nor o5;
o8 <= o7 nor o6;
Qbar <= o7;
Q <= o8;
end arch;
8 bit up counter code :
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity counter_8bit is
port(
clk :in std_logic;
output : out std_logic
);
end counter_8bit;
architecture arch of counter_8bit is
signal toninty : std_logic := '0';
signal Qout : std_logic_vector(7 downto 0) := "00000000";
component jk
port(
J : in STD_LOGIC;
K : in STD_LOGIC;
clk : in STD_LOGIC;
clr : in STD_LOGIC;
Q : out STD_LOGIC;
Qbar : out STD_LOGIC);
end component;
for all: jk use entity work.jk(arch);
signal j1,j2,j3,j4,j5,j6,j7,j8,k1,k2,k3,k4,k5,k6,k7,k8:std_logic := '0';
signal Qbar : std_logic;
signal clock : std_logic;
begin
toninty <= Qout(0) and Qout(1) and (not Qout(2)) and (not Qout(3)) and (not Qout(4)) and Qout(5) and Qout(6) and (not Qout(7));
clock <= not(clk);
j1 <= '1';
j2 <= Qout(0) after 1 ps;
j3 <= Qout(0) and Qout(1);
j4 <= j3 and Qout(2);
j5 <= j4 and Qout(3);
j6 <= j5 and Qout(4);
j7 <= j6 and Qout(5);
j8 <= j7 and Qout(6);
k1 <= '1';
k2 <= Qout(0) after 1 ps;
k3 <= (Qout(0) and Qout(1));
k4 <= (j3 and Qout(2));
k5 <= (j4 and Qout(3));
k6 <= (j5 and Qout(4));
k7 <= (j6 and Qout(5));
k8 <= (j7 and Qout(6));
a1 : jk
port map(
J => j1,
K => k1,
clk => clock,
Q => Qout(0),
Qbar => Qbar,
clr => toninty
);
a2 : jk
port map(
J => j2,
K => k2,
clk => clock,
Q => Qout(1),
Qbar => Qbar,
clr => toninty
);
.
.
.
.
a8 : jk
port map(
J => j8,
K => k8,
clk => clock,
Q => Qout(7),
Qbar => Qbar,
clr => toninty
);
output <= Qout;
end arch;
output example :
0 1 2 3 4 ... 99 0 1 2 ... 99 0 1 2 3 ...
I searched alot but didn't find a solution.it's compiled without any errors but I got UU in output and can't find the problem.
Right now I am working on a small project in Vivado, a Mealy FSM. The program must detect a 6 bits sequence 001011, and output "1" when the sequence is detected.
The code concerning the sequence detection is doing just fine, but besides that, it must also use Three Flip Flops: JK, D, and T.
Any advice or suggestions on how to add them?
Thank you for your time.
This is the FSM code:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity sequence is
port(
clk : in std_logic;
reset : in std_logic;
x: in std_logic;
z : out std_logic;
a : out std_logic;
b : out std_logic;
c : out std_logic;
d : out std_logic;
e : out std_logic;
f : out std_logic);
end sequence;
architecture behavioral of sequence is
type state_type is (Q0, Q1, Q2, Q3, Q4, Q5);
signal state, next_state : state_type;
begin
state_register: process (clk, reset)
begin
if (reset = '1') then --if reset is high, goto state Q0
state <= Q0;
elsif (clk'event and clk = '1') then --if not, and rising
state <= next_state; --edge, go to next state
end if;
end process;
next_state_func: process (x, state)
begin
case state is
when Q0 =>
if x = '0' then
next_state <= Q1;
else
next_state <= Q0;
end if;
when Q1 =>
if x = '0' then
next_state <= Q2;
else
next_state <= Q0;
end if;
when Q2 =>
if x = '1' then
next_state <= Q3;
else
next_state <= Q2;
end if;
when Q3 =>
if x ='0' then
next_state <= Q4;
else
next_state <= Q0;
end if;
when Q4 =>
if x = '1' then
next_state <= Q5;
else
next_state <= Q2;
end if;
when Q5 =>
if x = '1' then
next_state <= Q0;
else
next_state <= Q1;
end if;
end case;
end process;
-- This process controls the output of the sequence detector.
-- Each state has it's own output along with 'z' which indicates
-- the entire sequence 001011 has been detected.
output_func: process (x, state)
begin
case state is
when Q0 => z <= '0';
a <= '1';
b <= '0';
c <= '0';
d <= '0';
e <= '0';
f <= '0';
when Q1 => z <= '0';
a <= '0';
b <= '1';
c <= '0';
d <= '0';
e <= '0';
f <= '0';
when Q2 => z <= '0';
a <= '0';
b <= '0';
c <= '1';
d <= '0';
e <= '0';
f <= '0';
when Q3 => z <= '0';
a <= '0';
b <= '0';
c <= '0';
d <= '1';
e <= '0';
f <= '0';
when Q4 => z <= '0';
a <= '0';
b <= '0';
c <= '0';
d <= '0';
e <= '1';
f <= '0';
when Q5 => z <= '1';
a <= '0';
b <= '0';
c <= '0';
d <= '0';
e <= '0';
f <= '1';
end case;
end process;
end behavioral;
[1]: https://i.stack.imgur.com/pVwxL.jpg - and here is the table that contains the State Diagram Table of the FSM.
Your code is wrong. Take a look at the output_func process; this is combinatorial, and just decodes the current state, without looking at x. The a to f outputs aren't necessary, and are just a 6-bit decode of the current state - why? The z output is set when the current state is Q5, which isn't what you want - the whole process is redundant. You need to set z in your main FSM, when the current state is Q5, and x is 1 - ie. on the next_state <= Q0 transition.
On your actual question - you can't force selection of any particular F/F type with this code - the synthesiser will do whatever it wants, which means that it will implement the whole thing in D types, since JKs have been obsolete for the last 20 years. The same is probably true of T types. You need to start again, and pretend that you have a technology and a library with T, D, and JK. Write these yourself as separate entities, and re-write your code to instantiate these components, instead of allowing the synthesiser to infer them. Re-write your FSM to use JKs - the diagram you gave shows you how. In other words, derive the J and K inputs to each F/F. The z output can be a D-type. You should be able to fit in a T somewhere - I've left that as an exercise for you.
I am new to vhdl and trying to make testbench for multiplexer with 5 select lines but it gives me errors (the code is very long so I just copied the part which include the errors )
The code:
library ieee;
use ieee.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity Mux_4_to_1_tb is
end Mux_4_to_1_tb;
architecture tb of Mux_4_to_1_tb is
component Mux_4_to_1 is
port( clock : in std_logic;
D0, D1, D2, D3 : in std_logic; -- the data lines D0=A0 D1=A1 D2=B0 D3=B1
S0, S1, S2, S3, S4 : in std_logic; -- the selector switches
F : out std_logic_vector(2 downto 0)
);-- the output
end component;
constant clockperiod : time := 20 ns;
signal D0, D1, D2, D3, S0, S1 , S2, S3, S4 , F : std_logic;
signal selectors : std_logic_vector(4 downto 0);
begin
mapping: Mux_4_to_1 port map(D0, D1, D2, D3, S0, S1, S2, S3, S4, F );
--Concurrent processes
process
begin
S0 <= '0'; S1 <= '0'; S2 <= '0'; S3 <= '0'; S4 <= '0';wait for clockperiod;
S0 <= '0'; S1 <= '0'; S2 <= '0'; S3 <= '0'; S4 <= '1';wait for clockperiod;
S0 <= '0'; S1 <= '0'; S2 <= '0'; S3 <= '1'; S4 <= '0';wait for clockperiod;
S0 <= '0'; S1 <= '0'; S2 <= '0'; S3 <= '1'; S4 <= '1';wait for clockperiod;
S0 <= '0'; S1 <= '0'; S2 <= '1'; S3 <= '0'; S4 <= '0';wait for clockperiod;
S0 <= '0'; S1 <= '0'; S2 <= '1'; S3 <= '0'; S4 <= '1';wait for clockperiod;
S0 <= '0'; S1 <= '0'; S2 <= '1'; S3 <= '1'; S4 <= '0';wait for clockperiod;
S0 <= '0'; S1 <= '0'; S2 <= '1'; S3 <= '1'; S4 <= '1';wait for clockperiod;
S0 <= '0'; S1 <= '1'; S2 <= '0'; S3 <= '0'; S4 <= '0';wait for clockperiod;
S0 <= '0'; S1 <= '1'; S2 <= '0'; S3 <= '0'; S4 <= '1';wait for clockperiod;
S0 <= '0'; S1 <= '1'; S2 <= '0'; S3 <= '1'; S4 <= '0';wait for clockperiod;
S0 <= '0'; S1 <= '1'; S2 <= '0'; S3 <= '1'; S4 <= '1';wait for clockperiod;
S0 <= '0'; S1 <= '1'; S2 <= '1'; S3 <= '0'; S4 <= '0';wait for clockperiod;
S0 <= '0'; S1 <= '1'; S2 <= '1'; S3 <= '0'; S4 <= '1';wait for clockperiod;
S0 <= '0'; S1 <= '1'; S2 <= '1'; S3 <= '1'; S4 <= '0';wait for clockperiod;
S0 <= '0'; S1 <= '1'; S2 <= '1'; S3 <= '1'; S4 <= '1';wait for clockperiod;
S0 <= '1'; S1 <= '0'; S2 <= '0'; S3 <= '0'; S4 <= '0';wait for clockperiod;
end process;
process(S4, S3, S2, S1, S0)
begin
selectors <= S0&S1&S2&S3&S4;
end process;
process
begin
--The "assert" keyword allows you to test certain
--conditions. In other words, the point of assertion is
--to allow you to inspect what you expect.
--Two test cases are presented here. Feel free
--to add your own cases.
--TEST 1
D0 <= '0';
D1 <= '1';
D2 <= '0';
D3 <= '1';
wait for clockperiod;
case selectors is
when "00000" =>
assert(F => "000") report "Error 1: 00000" severity error;
Error:
** Error: E:\OneDrive\Engineering\Digital Circuit Design\TestBench.vhd(70): (vcom-1581) No feasible entries for infix operator '='.** Error: E:\OneDrive\Engineering\Digital Circuit Design\TestBench.vhd(70): Type error resolving infix expression "=" as type std.STANDARD.BOOLEAN.
The error point me to the line with the assert word.
Also i get this error at the end of the code
code:
when others =>
assert true;
end case;
end process;
end tb;
Error:
** Error: E:\OneDrive\Engineering\Digital Circuit Design\TestBench.vhd(229): VHDL Compiler exiting
The error point me to the last line here.
You're not providing any insight into how this testbench is supposed to operate without revealing the contents of Mux_4_to_1.
There are two things wrong with the assertion statement condition:
assert(F => "000")
F is declared as type std_logic which is not an array type and can't be compared to a string value (which would have an array type determinable by context). Also the relational operator should be >= and not =>, read as 'greater than or equal to'. => is a delimiter used in association.
Changing the relational operator and changing the declaration for F:
signal D0, D1, D2, D3, S0, S1 , S2, S3, S4 : std_logic; -- , F : std_logic;
signal F: std_logic_vector (2 downto 0);
generate an error telling us F can't be associated with S4, telling us you have a parameter list error. You don't have enough parameters. It's not an error to not provide an association for outputs which is why it wasn't noticed before, although the reader might assume you changed the declaration of F to get rid of that error a priori.
Adding a signal declaration for a clock:
constant clockperiod : time := 20 ns;
signal clock: std_logic;
and adding an association:
begin
-- mapping: Mux_4_to_1 port map(D0, D1, D2, D3, S0, S1, S2, S3, S4, F );
mapping:
Mux_4_to_1
port map (
clock => clock,
D0 => D0,
D1 => D1,
D2 => D2,
D3 => D3,
S0 => S0,
S1 => S1,
S2 => S2,
S3 => S3,
S4 => S4,
F => F
);
allows your code to analyze(by concatenating the code found with the others choice to the end of the VHDL code, you don't provide a Minimal, Complete and Verifiable example).
NOTES:
clock is not shown driven in the change description and if needed for your tests should be driven by the testbench.
Formal association is shown in the port map for the instantation of Mux_4_to_1, it allows you to see missing or wrong formal to actual port associations.
Superfluous parentheses surrounding conditions may obscure errors. They are only legal if the expression they contain is legal without them. It can change the error message you see. The lack of a proper relational operator results in a syntax error.
Hi I am a new Xilinx user and been having trouble with how to write stimulus/simulate in a test bench. My output(Kd) isn't giving me any sensible values and gives 'u' for the first few clock cycles before moving and staying at '1' throughout.
Not sure if I have written the correct stimulus but hoping someone would help me out here!
My VHDL code
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity codeFig2b is
Port ( R0 : in STD_LOGIC;
R1 : in STD_LOGIC;
R2 : in STD_LOGIC;
R3 : in STD_LOGIC;
Kd : out STD_LOGIC;
clock : in STD_LOGIC);
end codeFig2b;
architecture Behavioral of codeFig2b is
signal Qa, Qb: STD_LOGIC;
begin
process(clock, R0, R1, R2, R3)
begin
if clock = '1' and clock'event then
Qa <= (R0 or R1 or R2 or R3) or (Qa and Qb);
Qb <= Qa;
end if;
end process;
Kd <= Qa and Qb;
end Behavioral;
My Testbench ##
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY codeFig2b_test IS
END codeFig2b_test;
ARCHITECTURE behavior OF codeFig2b_test IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT codeFig2b
PORT(
R0 : IN std_logic;
R1 : IN std_logic;
R2 : IN std_logic;
R3 : IN std_logic;
Kd : OUT std_logic;
clock : IN std_logic
);
END COMPONENT;
--Inputs
signal R0 : std_logic := '0';
signal R1 : std_logic := '0';
signal R2 : std_logic := '0';
signal R3 : std_logic := '0';
signal clock : std_logic := '0';
--Outputs
signal Kd : std_logic;
-- Clock period definitions
constant clock_period : time := 100 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: codeFig2b PORT MAP (
R0 => R0,
R1 => R1,
R2 => R2,
R3 => R3,
Kd => Kd,
clock => clock
);
-- Clock process definitions
clock_process :process
begin
clock <= '0';
wait for clock_period/2;
clock <= '1';
wait for clock_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
R0 <= '0';
R1 <= '0';
R2 <= '0';
R3 <= '0';
wait for 100 ns;
R0 <= '0';
R1 <= '0';
R2 <= '0';
R3 <= '1';
wait for 100 ns;
R0 <= '0';
R1 <= '0';
R2 <= '1';
R3 <= '0';
wait for 100 ns;
R0 <= '0';
R1 <= '0';
R2 <= '1';
R3 <= '1';
wait for 100 ns;
R0 <= '0';
R1 <= '1';
R2 <= '0';
R3 <= '0';
wait for 100 ns;
R0 <= '0';
R1 <= '1';
R2 <= '0';
R3 <= '1';
wait for 100 ns;
R0 <= '0';
R1 <= '1';
R2 <= '1';
R3 <= '0';
wait for 100 ns;
R0 <= '0';
R1 <= '1';
R2 <= '1';
R3 <= '1';
wait for 100 ns;
R0 <= '1';
R1 <= '0';
R2 <= '0';
R3 <= '0';
wait for 100 ns;
R0 <= '1';
R1 <= '0';
R2 <= '0';
R3 <= '1';
wait for 100 ns;
R0 <= '1';
R1 <= '0';
R2 <= '1';
R3 <= '0';
wait for 100 ns;
R0 <= '1';
R1 <= '0';
R2 <= '1';
R3 <= '1';
wait for 100 ns;
R0 <= '1';
R1 <= '1';
R2 <= '0';
R3 <= '0';
wait for 100 ns;
R0 <= '1';
R1 <= '1';
R2 <= '0';
R3 <= '1';
wait for 100 ns;
R0 <= '1';
R1 <= '1';
R2 <= '1';
R3 <= '0';
wait for 100 ns;
R0 <= '1';
R1 <= '1';
R2 <= '1';
R3 <= '1';
wait for clock_period*10;
-- insert stimulus here
wait;
end process;
END;
This can be answered without simulating. Kd's output will go to a '1' and stay there.
process(clock, R0, R1, R2, R3)
begin
if clock = '1' and clock'event then
Qa <= (R0 or R1 or R2 or R3) or (Qa and Qb);
Qb <= Qa;
end if;
end process;
Kd <= Qa and Qb;
Qa goes high for any of R0, R1, R2 or R2 or (Qa and Qb);
So once Qa and Qb goes high Qa stays high.
Qb goes high one clock after the first occurrence of Qa going high.
The way this happens is o consecutive '1' inputs on any of R0, R1, R2 or R3.
You clock period is 100 ns and your stimulus interval is too.
You have no stimulus following the first clock where all of R0, R1, R2 and R3 are all low at the same time to demonstrate.
Unfortunately the waveform image on your Xilinx post (iSIM output Unintialised, doesn't change states.) doesn't show QA and Qb to see that they both go high and stay there:
(clickable)
When you add them this point comes through:
clickable)
What you built is a sequential logic, meaning that the outputs depend on the previous hystory of the inputs/outputs. In your case we have Qa, and Qb which is the last value of Qa.
Keeping this in mind, the approach you have used in the testbench is not optimal, because you are trying every combination of the inputs without taking into account that the last Qa is actually important.
This is what happens:
Start : Qa = U Qb = U => Kb = U
Inputs 1: Qa = 1 Qb = U => Kb = U
Inputs 2: Qa = 1 Qb = 1 => Kb = 1
Inputs 3: Qa = 1 Qb = 1 => Kb = 1
Inputs 4: Qa = 1 Qb = 1 => Kb = 1
....
As soon as one of the Rs goes high, Qa is high. Given the order of your combinations of inputs, there is no case where Qa goes low again.
This means that after the second input combination, Qb gets a known value and Kb goes high.
Sensitivity list
This is not part of the answer but it's a consideration on the code you have written: you have put on the sensitivity list R0, R1, R2, R3 but, given what you have written after that, this is not necessary.
The process does something only if
if clock'event and clock = 1 then
this means that any event on the Rs are ignored. I'm sure that the synthetizer actually realizes that and ignores it, but it's a good practice to set a proper sensitivity list and, when possible, only use clocked processes for sequential logic and finite state machines.
I also suggest that you use the more readable rising_edge(clock) and falling_edge(clock) functions:
process(clock)
begin
if rising_edge(clock) then
Qa <= R0 or R1 or R2 or R3 or (Qa and Qb);
Qb <= Qa;
end if;
end process;
Signals and processes
Another thing you should know is how the process work: you are not assigning new values to the signals, but rather planning values for them. If you reprogram a certain signal you are just overwriting the previous planning, and the first value is never assigned. The values are finally assigned at the end of the process.
Here is a simple example:
-- Let's assume A = 0 and B = 0 at startup
clocked_process : process(clk)
begin
if rising_edge(clk) then
A <= '1';
B <= A;
A <= '0';
end if;
end process;
At the end B is still 0, this because A = 0 for the whole process and only gets a planned value of 1, actually never assigned because it is overwritten before the end of the process (in this specific case the synthetizer will ignore A <= '1' for the implementation).
Overwriting the planned value can be used to simplify the logic: what I usually do is setting some default values and then overwriting them only when I need to.
So, instead of writing
...
case A is
when "00" =>
B <= '0';
when "01" =>
B <= '0';
when "10" =>
B <= '0';
when "11" =>
B <= '1';
end case;
...
I write this (I may retain the case structure if I need it for other signals, typically in Finite State Machines):
...
B <= '0';
if A = "11" then
B <= '1';
end if;
...
For this simple examples the synthetizer may be able to infer the semplification. However, you should get used to think in logic level ports because the same thing written in two equivalent ways from a behavioral point of view, is actually implemented differently.