Design of the project implemented in Vivado too complex - vhdl

Question

enter image description hereThis is the second doubt I'm having about this project, consisting in the design and implementation of a syncronous mini - router. I'll share again my source file and my test bench. I tried to simulate on modelsim and thanks to your help, now it works (see the picture).enter image description hereenter image description here
TESTBENCH:
-- -------------------------
-- Libreria
-- -------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-- -------------------------
-- Entity
-- -------------------------
entity mini_router_tb is
end mini_router_tb;
-- -------------------------
-- Architecture
-- -------------------------
architecture arc of mini_router_tb is
-----------------------------------------------------------------------------------
-- Costanti di testbench
-----------------------------------------------------------------------------------
constant T_CLK : time := 10 ns; --- frequenza di clock: 100 MHz
-----------------------------------------------------------------------------------
-- Segnali di testbech
-----------------------------------------------------------------------------------
-- I segnali di input del testbench sono inizializzati per evitare il valore X all'inizio della simulazione
-- I segnali di outout non sono inizializzati perchè settati dal DUT
signal clk_tb : std_logic := '0'; -- segnale di clock, inizializzato a 0
signal reset_tb : std_logic := '0'; -- reset attivo basso sincrono
signal data1_tb : std_logic_vector(9 downto 0) := (others => '0');
signal req1_tb : std_logic:= '0';
signal grant1_tb : std_logic;
signal data2_tb : std_logic_vector(9 downto 0) := (others => '0');
signal req2_tb : std_logic:= '0';
signal grant2_tb : std_logic;
signal data_out_tb : std_logic_vector(7 downto 0);
signal valid_tb : std_logic;
signal end_sim : std_logic := '1'; -- segnale usato per terminare la simulazione quando non c'è più nulla da testare
-----------------------------------------------------------------------------------
-- Dichiarazione del componente da testare (DUT)
-----------------------------------------------------------------------------------
-- E' solo una dichiarazione del componente
-- che sarà instanziato dopo il begin collegando le porte
-- ai senali di testbench per i test
component mini_router is
port (
clk : in std_logic;
reset : in std_logic;
data1 : in std_logic_vector(9 downto 0);
req1 : in std_logic;
grant1 : out std_logic;
data2 : in std_logic_vector(9 downto 0);
req2 : in std_logic;
grant2 : out std_logic;
data_out : out std_logic_vector(7 downto 0);
valid : out std_logic
);
end component;
begin
-- Il clock si attiva e disattiva ogni T_CLK / 2 quando end_sim è alto.
-- Quando end_sim is è forzato basso, il clock si ferma e la simulazione termina.
clk_tb <= (not(clk_tb)and(end_sim)) after T_CLK/2;
-----------------------------------------------------------------------------------
-- Mini - Router instantiation
-----------------------------------------------------------------------------------
DUT : mini_router
port map (
clk => clk_tb,
reset => reset_tb,
data1 => data1_tb,
req1 => req1_tb,
grant1 => grant1_tb,
data2 => data2_tb,
req2 => req2_tb,
grant2 => grant2_tb,
data_out => data_out_tb,
valid => valid_tb
);
-- Processo usato per fare in modo che i segnali di testbench signals cambino in corrispondenza del fronte in salita del clock
stimuli_process: process(clk_tb, reset_tb)
variable t : integer := 0; -- variabile usata per contare i cicli di clock
begin
if (rising_edge(clk_tb)) then
case (t) is
-- CASO 1: RESET: gli output sono tutti a 0 indipendentemente dagli input
-- data1 = 5; req1=1
-- data2 = 5; req2=0
-- data_out = 0; valid=0
-- grant1 = 0;
-- grant2 = 0;
when 1 => data1_tb <= (9 downto 3 => '0') & "101";
data2_tb <= (9 downto 4 => '0') & "0101";
req1_tb <= '1' ; req2_tb<= '0';
-- CASO 2: UN SOLO REQ ALTO: data1 è propagato in uscita
-- data1 = 4; req1=1
-- data2 = 13; req2=0
-- data_out = 1; valid=1
-- grant1 = 1;
-- grant2 = 0;
when 2 => reset_tb <= '1';
data1_tb <= (9 downto 3 => '0') & "100";
data2_tb <= (9 downto 4 => '0') & "1101";
req1_tb <= '1' ; req2_tb<= '0';
-- CASO 3: UN SOLO REQ ALTO: data2 è propagato in uscita
-- data1 = 4; req1=0
-- data2 = 13; req2=1
-- data_out = 3; valid=1
-- grant1 = 0;
-- grant2 = 1;
when 3 => data1_tb <= (9 downto 3 => '0') & "100";
data2_tb <= (9 downto 4 => '0') & "1101";
req1_tb <= '0' ; req2_tb<= '1';
-- CASO 4: REQ ENTRAMBI ALTI E STESSO LIVELLO DI PRIORITA':
-- data conflict e applicazione dell'algoritmo Round Robin:
-- data1 propagato in uscita
-- data1 = 7; req1=1
-- data2 = 31; req2=1
-- data_out = 1; valid=1
-- grant1 = 1;
-- grant2 = 0;
when 4 => data1_tb <= (9 downto 5 => '0') & "00111";
data2_tb <= (9 downto 5 => '0') & "11111";
req1_tb <= '1' ; req2_tb<= '1';
-- CASO 5: REQ ENTRAMBI ALTI E DIVERSO LIVELLO DI PRIORITA':
-- data1 propagato in uscita
-- data1 = 23; req1=1
-- data2 = 29; req2=1
-- data_out = 5; valid=1
-- grant1 = 1;
-- grant2 = 0;
when 5 => data1_tb <= (9 downto 5 => '0') & "10111";
data2_tb <= (9 downto 5 => '0') & "11101";
req1_tb <= '1' ; req2_tb<= '1';
-- CASO 6: REQ ENTRAMBI ALTI E STESSO LIVELLO DI PRIORITA':
-- data conflict e applicazione dell'algoritmo Round Robin:
-- data2 propagato in uscita
-- data1 = 22; req1=1
-- data2 = 30; req2=1
-- data_out = 7; valid=1
-- grant1 = 0;
-- grant2 = 1;
when 6 => data1_tb <= (9 downto 5 => '0') & "10110";
data2_tb <= (9 downto 5 => '0') & "11110";
req1_tb <= '1' ; req2_tb<= '1';
-- CASO 7: REQ ENTRAMBI BASSI: nessun dato è propagato in uscita
-- data1 = 7; req1=0
-- data2 = 31; req2=0
-- data_out = 0; valid=0
-- grant1 = 0;
-- grant2 = 0;
when 7 => data1_tb <= (9 downto 5 => '0') & "00111";
data2_tb <= (9 downto 5 => '0') & "11111";
req1_tb <= '0' ; req2_tb<= '0';
-- CASO 8: REQ ENTRAMBI ALTI E DIVERSO LIVELLO DI PRIORITA':
-- data2 propagato in uscita
-- data1 = 28; req1=1
-- data2 = 13; req2=1
-- data_out = 3; valid=1
-- grant1 = 0;
-- grant2 = 1;
when 8 => data1_tb <= (9 downto 5 => '0') & "11100";
data2_tb <= (9 downto 4 => '0') & "1101";
req1_tb <= '1' ; req2_tb <= '1';
-- CASO 9: REQ ENTRAMBI ALTI E STESSO LIVELLO DI PRIORITA':
-- data conflict e applicazione dell'algoritmo Round Robin:
-- data1 propagato in uscita
-- data1 = 22; req1=1
-- data2 = 30; req2=1
-- data_out = 5; valid=1
-- grant1 = 1;
-- grant2 = 0;
when 9 => data1_tb <= (9 downto 5 => '0') & "10110"; --data1=22; data_out =5
data2_tb <= (9 downto 5 => '0') & "11110"; -- data2= 30; data_out non assunto=7
req1_tb <= '1' ; req2_tb<= '1';
-- CASO 10: REQ ENTRAMBI ALTI E STESSO LIVELLO DI PRIORITA':
-- data conflict e applicazione dell'algoritmo Round Robin:
-- data2 propagato in uscita
-- data1 = 22; req1=1
-- data2 = 30; req2=1
-- data_out = 7; valid=1
-- grant1 = 0;
-- grant2 = 1;
when 10 => data1_tb <= (9 downto 5 => '0') & "10110"; --data1=22; data_out non assunto =5
data2_tb <= (9 downto 5 => '0') & "11110"; -- data2= 30; data_out =7
req1_tb <= '1' ; req2_tb<= '1';
when 11 => end_sim <= '0'; -- La simulazione termina quando t=10.
when others => null; -- Si specifica che nulla accade negli altri casi.
end case;
t := t + 1;
end if;
end process;
end architecture;
SOURCE FILE:
- -------------------------
-- Libreria
-- -------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;
-- -------------------------
-- Entity
-- -------------------------
entity mini_router is
port (
clk : in std_logic;
reset : in std_logic; -- Reset asincrono attivo basso
data1 : in std_logic_vector(9 downto 0);
req1 : in std_logic;
grant1 : out std_logic;
data2 : in std_logic_vector(9 downto 0);
req2 : in std_logic;
grant2 : out std_logic;
data_out : out std_logic_vector(7 downto 0);
valid : out std_logic
);
end entity;
-- -------------------------
-- Architecture
-- -------------------------
architecture arch of mini_router is
signal aux : std_logic_vector(9 downto 0);
begin
mini_router: process(clk,reset)
variable r : std_logic:= '1';
begin
if reset = '0' then
aux <= (others => '0');
grant1 <= '0';
grant2 <= '0';
valid <= '0';
elsif rising_edge(clk) then
if (req1 xor req2) = '1' then
if req1 = '1' then
aux <= data1;
grant1 <= '1';
grant2 <= '0';
valid <= '1';
else
aux <= data2;
grant1 <= '0';
grant2 <= '1';
valid <= '1';
end if;
elsif (req1 and req2) = '1' then
if (unsigned(data1 (1 downto 0))) > (unsigned(data2 (1 downto 0))) then
aux <= data1;
grant1 <= '1';
grant2 <= '0';
valid <= '1';
elsif (unsigned(data1 (1 downto 0))) < (unsigned(data2 (1 downto 0))) then
aux <= data2;
grant1 <= '0';
grant2 <= '1';
valid <= '1';
elsif (unsigned(data1 (1 downto 0))) = (unsigned(data2 (1 downto 0))) then
if r = '1' then
aux <= data1;
grant1 <= '1';
grant2 <= '0';
valid <= '1';
r := not (r);
else
aux <= data2;
grant1 <= '0';
grant2 <= '1';
valid <= '1';
r := not (r);
end if;
end if;
elsif (req1 nor req2) = '1' then
aux <= (others => '0');
grant1 <= '0';
grant2 <= '0';
valid <= '0';
end if;
end if;
end process;
data_out <= aux(9 downto 2);
end architecture;
But then I tried to simulate and implement it in Xilinx Vivado. There were no warnings, so I think everything work well, but as you can see from the picture, the structure is really too complicated and (I think) not efficient. My doubt is: is the problem the fact that I use only if/else/eslsif for my code, without a component instantion? I looked for another possibile design for my project, but this I the only solution I could come up with. Have you got any suggestions for me?

Answer 1

Why do you think, your code is not efficient? In my opinion, the schematic does not give a hint in this direction.
But there are some items which could be improved:
You define a variable r (with an initialization value) which is used as a signal (first read and then written), so you should it define as a signal (with a reset value). You should use variables only, if the behavior cannot be modeled by a signal.
Aux(1 downto 0) are never used, so you should not define them.
Your structure is a deep if-elsif-else structure, as if there was a priority which has to be used for the checks. But there is no priority for the check of req1 and req2?!
A deep structure often causes bad timing in the way that you get long combinatorial paths through many components. You can check this by looking at a timing report of your design.
So I would create a signal “request <= req1 & req2” and then use a “case” construct for all the decisions.
For the check of data1/2(1 downto 0) I would create this signal in a combinatorial process:
'''
process (data1, data2, r)
begin
if (unsigned(data1 (1 downto 0))) > (unsigned(data2 (1 downto 0))) then
prio <= "00";
elsif (unsigned(data1 (1 downto 0))) < (unsigned(data2 (1 downto 0))) then
prio <= "01";
else
prio <= '1' & r;
end process;
'''
So again you could switch to a case statement.
After these changes you could look at the timing report again. As your design is small, it may be that the synthesis tool has the same ideas and did all of the improvements automatically. But at least your design would be easier to read and give a hint, that there is no priority for the checks you have implemented.