I am using external naming to instantiate the following code:
snapshot_inst : entity work.snapshot
port map (
clk => clk_400,
resampler0_data_i => << signal demod_deframe_gen(0).demod_inst.u_demod.ext.ext_timing_i : slv16_array(1 downto 0) >>,
resampler1_data_i => << signal demod_deframe_gen(1).demod_inst.u_demod.ext.ext_timing_i : slv16_array(1 downto 0) >>,
resampler2_data_i => << signal demod_deframe_gen(2).demod_inst.u_demod.ext.ext_timing_i : slv16_array(1 downto 0) >>,
resampler0_data_q => << signal demod_deframe_gen(0).demod_inst.u_demod.ext.ext_timing_q : slv16_array(1 downto 0) >>,
resampler1_data_q => << signal demod_deframe_gen(1).demod_inst.u_demod.ext.ext_timing_q : slv16_array(1 downto 0) >>,
resampler2_data_q => << signal demod_deframe_gen(2).demod_inst.u_demod.ext.ext_timing_q : slv16_array(1 downto 0) >>,
resampler0_valid => << signal demod_deframe_gen(0).demod_inst.u_demod.ext.ext_timing_valid : std_logic >>,
resampler1_valid => << signal demod_deframe_gen(1).demod_inst.u_demod.ext.ext_timing_valid : std_logic >>,
resampler2_valid => << signal demod_deframe_gen(2).demod_inst.u_demod.ext.ext_timing_valid : std_logic >>,
equalizer0_data_i => << signal demod_deframe_gen(0).demod_inst.u_demod.ext.ext_eq_i : std_logic_vector(15 downto 0) >>,
equalizer1_data_i => << signal demod_deframe_gen(1).demod_inst.u_demod.ext.ext_eq_i : std_logic_vector(15 downto 0) >>,
equalizer2_data_i => << signal demod_deframe_gen(2).demod_inst.u_demod.ext.ext_eq_i : std_logic_vector(15 downto 0) >>,
equalizer0_data_q => << signal demod_deframe_gen(0).demod_inst.u_demod.ext.ext_eq_q : std_logic_vector(15 downto 0) >>,
equalizer1_data_q => << signal demod_deframe_gen(1).demod_inst.u_demod.ext.ext_eq_q : std_logic_vector(15 downto 0) >>,
equalizer2_data_q => << signal demod_deframe_gen(2).demod_inst.u_demod.ext.ext_eq_q : std_logic_vector(15 downto 0) >>,
equalizer0_valid => << signal demod_deframe_gen(0).demod_inst.u_demod.ext.ext_eq_valid : std_logic >>,
equalizer1_valid => << signal demod_deframe_gen(1).demod_inst.u_demod.ext.ext_eq_valid : std_logic >>,
equalizer2_valid => << signal demod_deframe_gen(2).demod_inst.u_demod.ext.ext_eq_valid : std_logic >>,
phased0_data_i => << signal demod_deframe_gen(0).demod_inst.u_demod.ext.ext_carrier_i : std_logic_vector(15 downto 0) >>,
phased1_data_i => << signal demod_deframe_gen(1).demod_inst.u_demod.ext.ext_carrier_i : std_logic_vector(15 downto 0) >>,
phased2_data_i => << signal demod_deframe_gen(2).demod_inst.u_demod.ext.ext_carrier_i : std_logic_vector(15 downto 0) >>,
phased0_data_q => << signal demod_deframe_gen(0).demod_inst.u_demod.ext.ext_carrier_q : std_logic_vector(15 downto 0) >>,
phased1_data_q => << signal demod_deframe_gen(1).demod_inst.u_demod.ext.ext_carrier_q : std_logic_vector(15 downto 0) >>,
phased2_data_q => << signal demod_deframe_gen(2).demod_inst.u_demod.ext.ext_carrier_q : std_logic_vector(15 downto 0) >>,
phased0_valid => << signal demod_deframe_gen(2).demod_inst.u_demod.ext.ext_carrier_valid : std_logic >>,
phased1_valid => << signal demod_deframe_gen(2).demod_inst.u_demod.ext.ext_carrier_valid : std_logic >>,
phased2_valid => << signal demod_deframe_gen(2).demod_inst.u_demod.ext.ext_carrier_valid : std_logic >>,
up_bus_in => up_bus_in,
up_bus_out => up_bus_outs(9)
);
As you can see, there is a lot of duplication in my referencing. Is there a way to do something like:
alias demod(x) is demod_deframe_gen(x).demod_inst.u_demod.ext -- Aliases a block, not a signal
That way I can shorten all of my external naming references?
What the OP is looking for is something to abstract and simplify the external_pathname of an external name.
If it were supported by VHDL, it could look something like the following, however, this fails both the OP's example in Xilinx and my test case (which requires a "." as the first path element).
alias demod0 is demod_deframe_gen(0).demod_inst.u_demod.ext ;
alias demod1 is demod_deframe_gen(1).demod_inst.u_demod.ext ;
alias demod2 is demod_deframe_gen(2).demod_inst.u_demod.ext ;
. . .
snapshot_inst : entity work.snapshot
port map (
clk => clk_400,
resampler0_data_i => << signal demod0.ext_timing_i : slv16_array(1 downto 0) >>,
resampler1_data_i => << signal demod1.ext_timing_i : slv16_array(1 downto 0) >>,
resampler2_data_i => << signal demod2.ext_timing_i : slv16_array(1 downto 0) >>
There is no question that a capability of this sort is needed in the language. I have added it to the following VHDL language issue:
https://gitlab.com/IEEE-P1076/VHDL-Issues/-/issues/115
Related
I was writing a code for a circuit involving three 7segment displays and a mux with selection inputs to select which character appears on the displays
library ieee;
use ieee.std_logic_1164.all;
entity e_my is
port(SW : in std_logic_vector(9 downto 0);
LEDR : out std_logic_vector(9 downto 0);
HEX0, HEX1, HEX2 : out std_logic_vector(0 to 6));
end entity e_my;
architecture a_my of e_my is
component e_my_2bit3to1mux is
port(slv_u, slv_S : in std_logic_vector(1 downto 0);
slv_v, slv_w : in std_logic_vector(1 downto 0);
slv_m : out std_logic_vector(1 downto 0));
end component;
component e_my_7segdec is
port(slv_C : in std_logic_vector(1 downto 0);
slv_display: out std_logic_vector(0 to 6));
end component;
signal slv_ch_Sel_int : std_logic_vector(1 downto 0);
signal slv_ch1_int,slv_ch2_int,slv_ch3_int : std_logic_vector(1 downto 0);
signal slv_H2_Ch_int,slv_H1_Ch_int, slv_H0_Ch_int : std_logic_vector(1 downto 0);
begin
LEDR <= SW;
slv_ch_Sel_int <= SW(9 downto 8);
slv_ch1_int <= SW(5 downto 4);
slv_ch2_int <= Sw(3 downto 2);
slv_ch3_int <= SW(1 downto 0);
I_M2: e_my_2bit3to1mux port map (slv_S => slv_ch_Sel_int,
slv_u => slv_ch1_int,
slv_v => slv_ch2_int,
slv_w => slv_ch3_int,
slv_m => slv_H2_Ch_int);
I_M1: e_my_2bit3to1mux port map (slv_S => slv_ch_Sel_int,
slv_u => slv_ch2_int,
slv_v => slv_ch3_int,
slv_w => slv_ch1_int,
slv_m => slv_H1_Ch_int);
I_M0: e_my_2bit3to1mux port map (slv_S => slv_ch_Sel_int,
slv_u => slv_ch3_int,
slv_v => slv_ch1_int,
slv_w => slv_ch2_int,
slv_m => slv_H0_Ch_int);
I_H2: e_my_7segdec port map (slv_H2_Ch_int, HEX2);
I_H1: e my_7segdec port map (slv_H1_Ch_int, HEX1);
I_H0: e_my_7segdec port map (slv_H0_Ch_int, HEX0);
end architecture a_my;
These are the errors.
Both are at the last line labeled I_H1. I dont understand. There is a 'port' near that text, but it still says its expecting.
Error (10500): VHDL syntax error at e_my.vhd(61) near text "my_7segdec"; expecting ";", or "port", or "generic"
Error (10500): VHDL syntax error at e_my.vhd(61) near text ";"; expecting "<="
I'm new to VHDL. My code now looks like this:
...
entity g14_lpm is
port ( i_clk : in std_logic;
i_rstb : in std_logic;
i_x : in std_logic_vector(31 downto 0);
i_y : in std_logic_vector(31 downto 0);
o_xx, o_yy : out std_logic_vector(64 downto 0)
);
end g14_lpm;
architecture arc of g14_lpm is
signal r_x : signed(31 downto 0);
signal r_y : signed(31 downto 0);
signal xx : signed(63 downto 0);
signal yy : signed(63 downto 0);
signal xy : signed(53 downto 0);
component LPM_MULT
...
port ( DATAA : in std_logic_vector(LPM_WIDTHA-1 downto 0);
DATAB : in std_logic_vector(LPM_WIDTHB-1 downto 0);
ACLR : in std_logic := '0';
CLOCK : in std_logic := '0';
CLKEN : in std_logic := '1';
RESULT : out std_logic_vector(LPM_WIDTHP-1 downto 0));
end component;
begin
------------------------COMPONENT INSTANTIATION---------------------------------
mult1 : LPM_MULT generic map (
LPM_WIDTHA => 32,
LPM_WIDTHB => 32,
LPM_WIDTHP => 64,
LPM_REPRESENTATION => "SIGNED",
LPM_PIPELINE => 4
)
--ERROR IS HERE↓
port map ( DATAA => i_x, DATAB => i_x, CLOCK => i_clk, RESULT => xx );
--ERROR IS HERE↑
...
p_mult : process (i_clk, i_rstb)
begin
...
elsif (rising_edge(i_clk)) then
r_x <= signed(i_x);
r_y <= signed(i_y);
o_xx <= std_logic_vector ('0' & xx - yy);
o_yy <= std_logic_vector (r_X*r_y & '0');
end if;
end process p_mult;
end arc;
And I am getting two errors at line 49, which is highlighted, saying type of identifier "xx" does not agree with its usage "std_logic_vector" type and cannot associate formal port "RESULT" of mode "out" with an expression.
I'm not sure what to change for this part, a significant portion of the code is provided in the manual.
How do I fix this?
Either use a helper signal
signal result : std_logic_vector(63 downto 0);
port map (
DATAA => i_x,
DATAB => i_x,
CLOCK => i_clk,
RESULT => result
);
xx <= signed(result);
or maybe they can be cast directly - never tried to be honest - like
port map (
DATAA => i_x,
DATAB => i_x,
CLOCK => i_clk,
signed(RESULT) => xx
);
as mentioned here
I got top module including sub-modules instantiated in testbench file. The sub-modules are pretty free on their own, therefore when I am testing the top module, I need to introduce only few signals and track few outputs, but the top module has many other ports.
May I provide some "default"/"undefined" signal (and sink) to those pins (not regarding their size, type)?
There are 2 ways I solve that right now, either take out the sub-module to test it (well, but I want to test it within top module) or write appropriate "zero" inputs for inputs and introduce signals for outputs (lot of work as well).
using VHDL with Vivado 2015
alright, so this is the testbench
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
entity tb_FIR_v0_3 is
end tb_FIR_v0_3;
architecture Behavioral of tb_FIR_v0_3 is
shared variable C_S00_AXI_DATA_WIDTH : integer := 32;
shared variable C_S00_AXI_ADDR_WIDTH : integer := 7;
component FIR_v0_3 is
generic (
C_S00_AXI_DATA_WIDTH : integer := 32;
C_S00_AXI_ADDR_WIDTH : integer := 7
);
port (
fir_clk : in std_logic;
fir_x_in : in std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0);
fir_y_out : out std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0);
fir_d_out : out std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0);
-- User ports ends
s00_axi_aclk : in std_logic;
s00_axi_aresetn : in std_logic;
s00_axi_awaddr : in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0);
s00_axi_awprot : in std_logic_vector(2 downto 0);
s00_axi_awvalid : in std_logic;
s00_axi_awready : out std_logic;
s00_axi_wdata : in std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0);
s00_axi_wstrb : in std_logic_vector((C_S00_AXI_DATA_WIDTH/8)-1 downto 0);
s00_axi_wvalid : in std_logic;
s00_axi_wready : out std_logic;
s00_axi_bresp : out std_logic_vector(1 downto 0);
s00_axi_bvalid : out std_logic;
s00_axi_bready : in std_logic;
s00_axi_araddr : in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0);
s00_axi_arprot : in std_logic_vector(2 downto 0);
s00_axi_arvalid : in std_logic;
s00_axi_arready : out std_logic;
s00_axi_rdata : out std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0);
s00_axi_rresp : out std_logic_vector(1 downto 0);
s00_axi_rvalid : out std_logic;
s00_axi_rready : in std_logic
);
end component FIR_v0_3;
signal e_clk : std_logic := '1' ;
signal e_reset : std_logic := '1' ;
signal e_x_in : std_logic_vector (31 downto 0);
signal e_y_out : std_logic_vector (31 downto 0);
signal e_d_out : std_logic_vector (31 downto 0);
signal s00_axi_awready : std_logic;
signal s00_axi_wready : std_logic;
signal s00_axi_bresp : std_logic_vector(1 downto 0);
signal s00_axi_bvalid : std_logic;
signal s00_axi_arready : std_logic;
signal s00_axi_rdata : std_logic_vector(32-1 downto 0);
signal s00_axi_rresp : std_logic_vector(1 downto 0);
signal s00_axi_rvalid : std_logic;
signal s00_axi_aclk : std_logic := '0';
signal s00_axi_aresetn : std_logic;
signal s00_axi_awaddr : std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0);
signal s00_axi_awprot : std_logic_vector(2 downto 0);
signal s00_axi_awvalid : std_logic := '0';
signal s00_axi_wdata : std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0);
signal s00_axi_wstrb : std_logic_vector((C_S00_AXI_DATA_WIDTH/8)-1 downto 0);
signal s00_axi_wvalid : std_logic := '0';
signal s00_axi_bready : std_logic := '0';
signal s00_axi_araddr : std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0);
signal s00_axi_arprot : std_logic_vector(2 downto 0);
signal s00_axi_arvalid : std_logic := '0';
signal s00_axi_rready : std_logic := '0';
begin
inst_FIR_v0_3 : FIR_v0_3
generic map (
C_S00_AXI_DATA_WIDTH => 32,
C_S00_AXI_ADDR_WIDTH => 7
)
port map (
-- Users to add ports here
fir_clk => e_clk,
fir_x_in => e_x_in,
fir_y_out => e_y_out,
fir_d_out => e_d_out,
-- Ports of Axi Slave Bus Interface S00_AXI
s00_axi_aclk => s00_axi_aclk,
s00_axi_aresetn => e_reset,
s00_axi_awaddr => ( others => '0' ),
s00_axi_awprot => ( others => '0' ),
s00_axi_awvalid => s00_axi_awvalid,
s00_axi_awready => s00_axi_awready,
s00_axi_wdata => ( others => '0' ),
s00_axi_wstrb => ( others => '0' ),
s00_axi_wvalid => s00_axi_wvalid,
s00_axi_wready => s00_axi_wready,
s00_axi_bresp => s00_axi_bresp,
s00_axi_bvalid => s00_axi_bvalid,
s00_axi_bready => s00_axi_bready,
s00_axi_araddr => ( others => '0' ),
s00_axi_arprot => ( others => '0' ),
s00_axi_arvalid => s00_axi_arvalid,
s00_axi_arready => s00_axi_arready,
s00_axi_rdata => s00_axi_rdata,
s00_axi_rresp => s00_axi_rresp,
s00_axi_rvalid => s00_axi_rvalid,
s00_axi_rready => s00_axi_rready
);
process
variable count : integer := 0;
begin
if ( count = 0 ) then
-- e_reset <= '0'; -- VALUES NOT INITIATED PROPERLY, FUCKER ? ... With the non-stop, pop pop and stainless steel (DMX)
e_x_in <= x"00000000";
end if;
if ( count = 3 ) then
-- e_reset <= '1';
end if;
if ( count = 3 ) then
e_x_in <= x"00000001";
end if;
if ( count = 5 ) then
e_x_in <= x"00000000";
end if;
if ( count = 8 ) then
e_x_in <= x"00000000";
end if;
e_clk <= not(e_clk);
wait for 0.5 ns;
count := count + 1;
if( (count = 60) ) then
count := 0;
end if;
end process;
end Behavioral;
I am too lazy to create signal for every AXI input/output ports and then connect them one by one. May I avoid somehow creating those 21 signals ...
signal s00_axi_awready : std_logic;
signal s00_axi_wready : std_logic;
signal s00_axi_bresp : std_logic_vector(1 downto 0);
signal s00_axi_bvalid : std_logic;
signal s00_axi_arready : std_logic;
....
...
and then connecting them ? Like this ...
s00_axi_wvalid => s00_axi_wvalid,
s00_axi_wready => s00_axi_wready,
s00_axi_bresp => s00_axi_bresp,
s00_axi_bvalid => s00_axi_bvalid,
s00_axi_bready => s00_axi_bready,
Is there any "universal" in/out signal that I would tie to pins that are not important, because I cant leave the ports of an instance unconnected (as far as I know and tried).
If I understand the question correctly, inputs in your port definition can have default values, and outputs can be left unconnected in an instantiation. For example:
entity ShiftRegister is
Generic (
WIDTH : integer
);
Port (
clk : in STD_LOGIC;
enable : in STD_LOGIC := '1';
serial_in : in STD_LOGIC := '0';
parallel_out : out STD_LOGIC_VECTOR (WIDTH-1 downto 0);
);
end ShiftRegister;
...
SR : entity work.ShiftRegister
Generic map (
WIDTH : integer => 8
)
Port map(
clk => serial_clk,
serial_in => serial_data_in
);
In this example, the register will always be enabled, and the entity does not output anything. Not a very useful instantiation in this case, but I think this answers your question!
So I have the following VHDL code to implement an Nbit adder/subtractor using only a 2:1 mux, an inverter (flips bit), and a full adder. I am having issues connecting the carry out of an adder to the next ones carry in while having the first adder have a carry in of i_Control. Any help would be greatly appreciated :).
library IEEE;
use IEEE.std_logic_1164.all;
use work.all;
entity add_subtract is
generic(N : integer := 16);
port(i_M : in std_logic_vector(N-1 downto 0);
i_N : in std_logic_vector(N-1 downto 0);
i_Control : in std_logic_vector(N-1 downto 0);
o_S : out std_logic_vector(N-1 downto 0));
end add_subtract;
architecture structure of add_subtract is
component bit_adder
port(i_X : in std_logic;
i_Y : in std_logic;
i_Cin : in std_logic;
o_Ss : out std_logic;
o_Couts : out std_logic);
end component;
component inverter
port(i_A : in std_logic;
o_F : out std_logic);
end component;
component bit_mux
port(i_X : in std_logic;
i_Y : in std_logic;
i_S : in std_logic;
o_N : out std_logic);
end component;
signal compvalue, muxvalue, addervalue : std_logic_vector(N-1 downto 0);
signal sel, carry : std_logic_vector(N-1 downto 0);
signal k : integer := 0;
begin
carry(0) <= i_Control(0);
G1: for i in 0 to N-1 generate
one_comp: inverter
port map(i_A => i_N(i),
o_F => compvalue(i));
mux: bit_mux
port map(i_X => i_N(i),
i_Y => compvalue(i),
i_S => i_Control(i),
o_N => muxvalue(i));
struct_adder: bit_adder
port map(i_X => i_M(i),
i_Y => muxvalue(i),
i_Cin => carry(i),
o_Ss => o_S(i),
o_Couts => carry(i));
end generate;
end structure;
Make the carry array one longer:
signal carry : std_logic_vector(N downto 0); -- was N-1
and change this:
o_Couts => carry(i));
to this:
o_Couts => carry(i+1));
in your generate statement while leaving the i_Cin carry input association as is.
If the last carry out isn't conveyed through an output port the net will get eaten during synthesis.
I'm trying to create an m bit adder by instantiating multiple copies of the n bit adder using for/generate loop. This is my code so far, it fails to simulate by giving the error:
"Line 44: Not all partial formals of a_n have actual". The n bit adder is declared as component, I have successfully tested it and it works.
Please help by offering any suggestions to solve this problem
entity m_bit_adder is
generic (m : integer := 16; n : integer := 4);
Port ( A_m : in STD_LOGIC_VECTOR (m-1 downto 0);
B_m : in STD_LOGIC_VECTOR (m-1 downto 0);
Cin_m : in STD_LOGIC;
Cout_m : out STD_LOGIC;
S_m : out STD_LOGIC_VECTOR (m-1 downto 0));
end m_bit_adder;
architecture Behavioral of m_bit_adder is
component n_bit_adder is
generic (n_number : integer := 4);
Port ( A_n : in STD_LOGIC_vector(n-1 downto 0);
B_n : in STD_LOGIC_vector(n-1 downto 0);
Cin_n : in STD_LOGIC;
S_n : out STD_LOGIC_vector(n-1 downto 0);
Cout_n : out STD_LOGIC);
end component;
signal sig_m : std_logic_vector (m downto 0);
begin
m_bit_adder : for j in 0 to m-1 generate
n_bit : n_bit_adder generic map (n_number => n)
port map (
A_n(n-1) => A_m(j),
B_n(n-1)=> B_m(j),
S_n(n-1) => S_m(j),
Cin_n => sig_m(j),
Cout_n => sig_m(j+1)
);
end generate;
sig_m(0) <= Cin_m;
Cout_m <= sig_m(m);
end Behavioral;
This is my code for the n adder:
entity n_bit_adder is
generic (n : integer := 4);
Port ( A_n : in STD_LOGIC_vector(n-1 downto 0);
B_n : in STD_LOGIC_vector(n-1 downto 0);
Cin_n : in STD_LOGIC;
S_n : out STD_LOGIC_vector(n-1 downto 0);
Cout_n : out STD_LOGIC);
end n_bit_adder;
architecture Behavioral of n_bit_adder is
component adder
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
Cin : in STD_LOGIC;
S : out STD_LOGIC;
Cout : out STD_LOGIC);
end component;
signal sig_n : std_logic_vector (n downto 0);
begin
n_bit_adder : for i in 0 to n-1 generate
one_bit : adder
port map (
A => A_n(i),
B => B_n(i),
S => S_n(i),
Cin => sig_n(i),
Cout => sig_n(i+1)
);
end generate;
sig_n(0) <= Cin_n;
Cout_n <= sig_n(n);
end Behavioral;
The n_bit_adder is instantiated using only a single bit of the formal side with A_n(n-1) in:
n_bit : n_bit_adder generic map (n_number => n)
port map (
A_n(n-1) => A_m(j),
....
But the component for n_bit_adder has as std_logic_vector for A_n with multiple bits in:
component n_bit_adder is
generic (n_number : integer := 4);
Port ( A_n : in STD_LOGIC_vector(n-1 downto 0);
...
So for a std_logic_vector(3 downto 0) then A_n(2 downto 0) are not used on the formal side (left side) of the mapping, which is also what the error message says in "Not all partial formals of a_n have actual".
Note also, that it looks like different names n_number and n are used in component for generic and std_logic_vector length on ports.