I have an Intel Altera Arria ii gx fpga board and I want to implement a project on software defined radio (SDR) using GNU Radio on it. Is it possible to load USRP Hardware Driver (FPGA build) provided by Ettus Research If possible how can I do it If not is there any other way to implement SDR on FPGA
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I have an altera DE2 cyclone-ii fpga board and I want to implement a project on software defined radio(SDR) using GNU Radio on it.Is it possible to load USRP Hardware Driver(FPGA build) provided by Ettus Research.If possible how can I do it.If not is there any other way to implement SDR on FPGA :)
You probably will need some daughter boards to do the front-end processing, which handles the high-frequency signals.
You can use an RTL as a daughter board and with some changes at the USRP code (mostly on the signal reception) you will be able to build your own SDR.
I want to load riscv on zcu102 xilinx board. I looked at various sites, they have codes for other specific boards and I am not quite sure how to port it.
Since I am a beginner, can you provide some starting point for it ?
I tried lowrisc implementation but i am not able to port it to zcu102.
Sorry for ambiguity. I wanted to run riscv soc platform such as lowrisc on fpga. But the code given in their github is optimized for nexy4 ddr board. And I am getting issues for converting it to zcu102. So, I was asking if there is some steps I can follow ? Like list of interfaces need to be changed ?
Risc-V is not a processor.
Risc-V is an Instructions Set (ISA) implemented by some processors.
Then if you want to "load" a Risc-V processor you have to choose one, then synthetize it with your FPGA tools (Vivado for Xilinx).
Here a list of Risc-V cores on Risc-v fondation website.
You can try the Instant Soc from FPGA Cores.
The compiler builds a soc including this RISC-V processor and UARTs, I2Cs etc directly from C++. All peripherals are defined as C++ objects. Very easy to use.
I have mostly used it with Artix to interface the AXIS streams on the Ethernet cores.
I am looking for HPS to FPGA custom component integrations guideline using Qsys. I have De0 nano SoC board. I am new to SoC FPGA programming. I still could not found a material or tutorial for HPS to custom VHDL or Verilog component integration. I need to get to know what are the connections that I should make and how to/ where to declare them in C code on ARM processor and the entity of the FPGA custom designed component. Can any body post some links.
I have read following tutorials from Altera.
Avalon Interface Specifications pdf,
ARM_A9_intro_intelfpga pdf,
Intel_FPGA_Monitor_Program_ARM pdf,
making qsys component pdf,
Using_GIC - ARM HPS pdf,
External_Bus_to_Avalon_Bridge -nios II pdf,
Avalon_to_External_Bus_Bridge nios II pdf,
DE0-Nano-SoC_Computer_ARM pdf.
On the FPGA side Quartus is used to instantiate the HPS as an IP Core in QSys. HPS-to-FPGA bridges can be enabled and IP connected to it. Either do it in QSys or export the bus via a bridge into a wrapper VHDL or Verilog design.
There is a QSys section in Volume 1 of the Quartus Handbook:
https://www.altera.com/products/design-software/fpga-design/quartus-prime/support.html
On the HPS side, you have to generate a new Preloader from the Quartus output. You will have to write a Linux kernel driver for you device and probably create a DeviceTree entry. You can do simple tests with the mw/md commands in UBoot or Linux userspace e.g. by mmapping /dev/mem.
RocketBoards.org is a great resource. Your board is compatible with Atlas-SoC Development Platform: https://rocketboards.org/foswiki/view/Documentation/AtlasSoCDevelopmentPlatform#Getting_Started
I have a PCIe generated core / endpoint with the xilinx core generator tool for a spartan6 fpga on a development board which I have modified a bit to enable MSI and send these every couple of seconds.
Also, I did a simple C kernel module on my linux desktop in which I plugged in the development board. This registers device, allocates memory, enables bus mastership for device and handles the interrupts etc.
What I want to do now is some DMA transfer from the board to the PC, and then will send an interrupt when finished, so that the cpu can go and read it. I'm not a Verilog expert, and the code I have doesn't seem to be capable of any DMA functions.
I couldn't find any relevant information online, so this is my last hope.
Original text from comment above:
Have you implemented a transaction layer above the generated PCIe core? Why don't you use a free PCIe core if your HDL skills are not so high? PCIe is a very big thing....
Yes, the Xilinx IPCore generator adds a very simple PIO interface ontop of the link layer to handle simple PIO transactioons. Note: PIO transaction are outdated and not allowed for new devices.
Currently I know two rather good IPCores:
XILLYBUS
free educational license
create the IPCore for your FPGA device online and download a netlist
free linux and windows drivers (the linux driver will be included in the standard kernel)
8-bit and 32-bit FIFO interface and a memory interface
linux-driver mapps FPGA to /dev/xillybus_read /dev/xillybus_write devices
RIFFA
I'm not sure if this core is still maintained
free driver
it has a strange interface with up to 12 FIFO channels
free HDL sources
All these cores require the Xilinx Core Generator to generate a PCIe core for your device/board. The core itself provides transaction handling, ...
My company is trying to build a pcb with an obsolete xilinx fpga (XC3042A) which is part of the XC3000 series chips. Does anyone have any experience programming the data to the chip? I'm looking for what software, hardware, etc. people have used.
I have programmed old Xilinx chips (XC4010XL) using a custom built interface to the ISA bus.
I used Turbo-C on a DOS box and a home-made ISA card with '245 (bidir transceiver) and a 74LS74 (dual flip flop D) for strobe signals on a slave parallel configuration.
It is not difficult to implement the same using a parallel port, for instance.
You should be able to find the programming specs from the Xilinx website. They provide documentation on the different methods used in programming their FPGA. It should be in their AppNotes. They have several modes - typically slave serial or select map (parallel). That means some sort of SPI flash, or parallel flash, or JTAG.
If you look around, you may find schematics for a DIY programming cable too! You can also interface a small micro, say a 8-bit PIC to handle the programming specs while you design your own custom interface to it or interface it to a SD card or something else.
The current Xilinx tools and cables will program old parts.
The XC3000 series does not use the JTAG interface, so you can not use the Xilinx programmer to download your configuration.
You can do so by either using an external EPROM or an embedded processor to download the code.
Take a look at this applications note from Xilinx:
http://www.xilinx.com/support/documentation/application_notes/xapp090.pdf
For daisy chain:
http://www.xilinx.com/support/documentation/application_notes/xapp091.pdf
It describes the data format as well as signal info for downloading the configuration file to the FPGA.
You can use older version of the Xilinx programmer from their web site and configure the devices, I believe the last version of the xilinx supporting the 3000 series was version 8 but I am not sure.
Check out FTDI. You might be able to convince them to go with some updated hardware. It's currently $150 CAD for USB + FPGA, and $80 CAD extra if you bundle it with a Manual. Plus shipping.
It even supports the free web kit available from the Xilinx website.