I'm trying to get GNU make to produce multiple outputs from a single input. The most simple example I can demonstrate is:
a b : test
cp $< $#
which, I believe, should copy the file test to the files name a and b. However, it only makes the file a, which seems to me to be contrary to the instructions listed here:
http://www.gnu.org/software/automake/manual/make/Multiple-Targets.html
Am I doing something wrong?
Thanks,
Tom
If you run a rule that depends on a, it will run your rule with $< as test and $# as a. If you run a rule that depends on b, $# will be b instead. If you make a rule above your current rule like:
all: a b
It will run the rules for a and b, which is that same rule twice. Otherwise, if your rule is the first in the file it will run it with the first target only, which is a
A small clarification to #MichaelMrozek's answer.
This:
a b : test
cp $< $#
Is exactly the same as:
a : test
cp $< $#
b : test
cp $< $#
a is the first target in the file, so it's the default target. Only the rule for a runs, since there's no dependency on b.
Like #MichaelMrozek said, you can add another rule, or you can run
make a b
Everything is OK. The manual says :
bigoutput littleoutput : text.g
generate text.g -$(subst output,,$#) > $#
is equivalent to
bigoutput : text.g
generate text.g -big > bigoutput
littleoutput : text.g
generate text.g -little > littleoutput
So your Makefile is also equivalent to
a : test
cp $< $#
b : test
cp $< $#
and when you'd entered the command 'make', the program defaulted to build the first target, i.e. 'a'.
Related
I'm trying to get Make to build some data analysis, where there are file lists controlled by one overall parameter.
To write it explicitly would be something like:
A_EXTS = a b c d e
B_EXTS = f g h i j
C_EXTS = k l m n o
A.dat : $(foreach EXT, ${A_EXTS}, prefix1_${EXT}.dat prefix2_${EXT}.dat)
python analyse.py $^ > $#
B.dat : $(foreach EXT, ${B_EXTS}, prefix1_${EXT}.dat prefix2_${EXT}.dat)
python analyse.py $^ > $#
C.dat : $(foreach EXT, ${C_EXTS}, prefix1_${EXT}.dat prefix2_${EXT}.dat)
python analyse.py $^ > $#
Obviously the only difference between the three rules is the A vs B vs C.
I thought to try something like
%.dat : $(foreach EXT, ${%_EXTS}, prefix1_${EXT}.dat prefix2_${EXT}.dat)
python analyse.py $^ > $#
…but that doesn't work; e.g. make B.dat runs the rule for B.dat but ignores the dependencies; $^ is set to the empty string.
The files starting prefix2_ are generated by another recipe, so I can't just specify them within the recipe, they need to be marked as dependencies here.
Is this possible to express these dependencies without repeating the same rule?
Well, you can't do it quite like you want to here, but it's not related to looking up variable names: it's because of expansion order.
Variables in targets and prerequisites are expanded when the makefile is parsed, but make doesn't expand the patterns in pattern rules until much later. That means when make expands the ${%_EXTS} variable as it parses the makefile, it has no idea what the value of % will be later when it's actually trying to build things.
You can use secondary expansion to delay expansion of variables until make's second pass where it is actually finding target names. I pulled the logic out into a separate variable and used call to make it a bit more readable:
.SECONDEXPANSION:
EXPANDDEPS = $(foreach EXT,${$1_EXTS},prefix1_${EXT}.dat prefix2_${EXT}.dat)
%.dat : $$(call EXPANDDEPS,$$*)
python analyse.py $^ > $#
I have the following makefile:
SHELL:/bin/bash
all: euro.n.{a,b}
euro.{a,b}:
touch euro.{a,b}
euro.n.{a,b}: euro.{a,b}
cat euro.a > euro.n.a
cat euro.b > euro.n.b
Now if I run make twice, the makefile won't recognize in the second run that the files euro.n.a and euro.n.b have already been created (and it will be executed again).
What is the problem?
What is the problem?
{a,b} is not syntax recognized by GNU make.
SHELL := /bin/bash (you missed = there) only affects the syntax of recipes.
One alternative solution:
SHELL := /bin/bash
all: $(addprefix euro.n.,a b)
euro.%:
touch $#
euro.n.% : euro.%
cp $< $#
I tried to make a makefile with patterns.
I want to have two variants:
when i write make it should just compile the list of files.
when i write make run it should run the respective files.
this is my current makefile:
files = test test1 test2
all: $(files)
$(files): % : %.scala
scalac $<
run: $(files)
$(files): % : %.scala
scala $<
now, regardless of whether i do make or make run it always executes the scala command and never scalac
You have a duplicate target:
$(files): % : %.scala
remove one of the targets (probably the second line was added by you)
Hopefully this is a very simple question. I have a makefile pattern rule that looks like this:
%.so : %.f %.pyf
f2py -c -L${LAPACK_DIR} ${GRASPLIBS} -m $* $^ ${SOURCES} --opt='-02' --f77flags='-fcray-pointer' >> silent.txt
I want the makefile to build a number of .so files, so I tried to get it to build two files (radgrd_py.so and lodiso_py.so) by doing this:
radgrd_py.so lodiso_py.so:
%.so : %.f %.pyf
f2py -c -L${LAPACK_DIR} ${GRASPLIBS} -m $* $^ ${SOURCES} --opt='-02' --f77flags='-fcray-pointer' >> silent.txt
and then tried this:
radgrd_py.so:
lodiso_py.so:
%.so : %.f %.pyf
f2py -c -L${LAPACK_DIR} ${GRASPLIBS} -m $* $^ ${SOURCES} --opt='-02' --f77flags='-fcray-pointer' >> silent.txt
But in each case, it only builds the first target that I specify. If I run 'make radgrd_py.so' it works fine, I'm just not sure how to specify a list of files that need to be built so I can just run 'make'.
The usual trick is to add a 'dummy' target as the first that depends on all targets you want to build when running a plain make:
all: radgrd_py.so lodiso_py.so
It is a convention to call this target 'all' or 'default'. For extra correctness, let make know that this is not a real file by adding this line to your Makefile:
.PHONY: all
Best way is to add:
.PHONY: all
.DEFAULT: all
all: radgrd_py.so lodiso_py.so
Explanations:
make uses the first target appearing when no .DEFAULT is specified.
.PHONY informs make that the targets (a coma-separated list, in fact) don't create any file or folder.
all: as proposed by schot
I'm currently learning how to use makefiles. But I'm struggling with % pattern rules. I've boiled down my failing makefile to this very simple example:
I fill an empty directory with:
echo aaa > a.in && echo bbb > b.in
A first makefile like this works very well:
a.out : a.in
cat $< > $#
as
make && echo *.out && cat *.out
returns
cat a.in > a.out
a.out
aaa
but when I try to use a pattern rule modifying the makefile as follows:
%.out : %.in
cat $< > $#
make then returns me:
make: *** No targets. Stop.
It seems like a very simple problem but I can't get to what I am missing...
If you have a makefile with no targets lists (only patterns), and you just type make, then you haven't told make that it should build anything specific, so it won't do anything.
A pattern rule doesn't mean "go find all the files that match this pattern and build them". A pattern rule tells make "if you need to find a way to build a file that matches this target pattern, then here's how you do it".
If you type make a.out so make knows that you want to build a target a.out, then make will use your pattern rule to build it.
Alternatively, you can add the target to your makefile, something like this:
.PHONY: all
all: a.out
%.out : %.in
cat $< > $#