I've found something for compiling text file as string variable:
Code:
objcopy --input binary --output elf64-x86-64 --binary-architecture i386 test.txt test.o
and i want to do it for each ./included_text/*.abc and then each of these files link.
I've find pre/post build steps but i can't find anything which will help me. Or you can explain how to do whole makefile if it's easier.
output:
text_files:= $(wildcard *.txt)
text_objects:=$(addsuffix .o,$(basename $(text_files)))
objects=$(text_objects) $(other_objects)
%.o: %.txt
objcopy --input binary $(OBJCOPY_FLAGS) $< $#
output: $(objects)
echo linking $# from $^
#ld ....
Related
I'm new to make. I have a bunch of FOO.32.asm and FOO.64.asm files in a directory. I'd like a Makefile that will assemble each of them to FOO.32.o or FOO.64.o as appropriate, then link each into FOO.32 or FOO.64 executables.
I think maybe static patterns are part of the answer, something like:
%.32.o : %.32.asm
nasm -f elf -gstabs $<
%.64.o : $.64.asm
nasm -f elf64 -gstabs $<
But I'm not sure how to specify the "ultimate" target -- the executables that will depend on the object files. I want to express something like the following:
%.32 : %.32.o
gcc -m32 -o %.32 %.o
%.64 : %.32.o
gcc -o %.64 %.o
Any ideas?
First find all the source files:
src32 := $(wildcard *.32.asm)
src64 := $(wildcard *.64.asm)
Next, create targets that depend on the object files, and have an initial rule that depends on both so both are built by default:
all: output.32 output.64
output.32 : $(src32:.asm=.o)
gcc -m32 -o $# $^
output.64 : $(src64:.asm=.o)
gcc -o $# $^
And add in your pattern rules above:
%.32.o : %.32.asm
nasm -f elf -gstabs $<
%.64.o : %.64.asm
nasm -f elf64 -gstabs $<
ETA
If you want to create one binary per object file that's simple too:
src32 := $(wildcard *.32.asm)
src64 := $(wildcard *.64.asm)
all: $(src32:.asm=) $(src64:.asm=) $(src32:.asm=.o) $(src64:.asm=.o)
%.32 : %.32.o
gcc -m32 -o $# $^
%.64 : %.64.o
gcc -o $# $^
%.32.o : %.32.asm
nasm -f elf -gstabs $<
%.64.o : %.64.asm
nasm -f elf64 -gstabs $<
That's it! There are fancier ways to do this that allows you to use only one pattern rule to build objects and one pattern rule to build all executables, but the above is simple and understandable.
If you want to keep the object files to investigate them, you need to add the object files to the all target (or, some target: it doesn't have to be all), else make will consider them intermediate files and will automatically remove them. By listing the object files as explicit prerequisites, make knows you want to keep them around.
I took a makefile from a previous project that compiles programs for an avr microcontroller. I ran into some problems with what IO ports/data directional addresses I was setting which was causing the microcontroller to fault and reset. Because of this I wanted to add a step in my makefile to have it generate the pre-proccessed files and then compile from these preprocessed files. I'm not too familiar with how rules/dependencies work in makefiles so I've made, what I believe is, a simple mistake in my understanding of how makefiles work. My rules to make the preprocessed files/object files and eventually the .elf file must be wrong. Up until I added the steps which attempted to create the preprocessed files creating the .elf file work fine. What is my simple mistake/understanding in how rules/dependencies work in make?
How I view this working is when I ask to make all it sees that it has a dependency of led.elf. To create this it has the dependency of the preprocessed files based on the line of $(OUTPUT).elf: $(PROCESS_FILES) so it starts with this line. When I try to make all however I get the error make: *** No rule to make target 'main.c', needed by 'main.e'. Stop. and I don't understand why. Can anyone help my understanding in make files?
SRC_FILES=\
main.c led.c comm.c
#Object files
PROCESS_FILES=$(SRC_FILES:.c=.e)
OBJ_FILES=$(PROCESS_FILES:.e=.o)
#Directories where to look for include files
INC_DIRS=\
-I. \
#Output file name
OUTPUT=led
#Programmer and port
PROG=dragon_isp
PORT=usb
#Debugging host and port
DHOST=localhost
DPORT=6423
#Compiler related params
MCU=atmega2560
CC=avr-gcc
OBJCOPY=avr-objcopy
CFLAGS= -mcall-prologues -std=gnu99 -funsigned-char -funsigned bitfields \
-fpack-struct -fshort-enums -mmcu=$(MCU) -Wall -Wstrict-prototypes \
$(INC_DIRS)
#Optimization level
CFLAGS+=-Os
#Debug info
CFLAGS+=-gdwarf-2
#Generate hex file ready to upload
all: $(OUTPUT).elf
$(OBJCOPY) -R .eeprom -O ihex $(OUTPUT).elf $(OUTPUT).hex
#Link output files
$(OUTPUT).elf: $(PROCESS_FILES)
$(CC) $(CFLAGS) $(OBJ_FILES) -o $(OUTPUT).elf -Wl,-Map,$(OUTPUT).map
#Create object files
$(PROCESS_FILES): %.e : %.c
$(CC) -E $(CFLAGS) $< -o $#
$(OBJ_FILES): %.o : %.e
$(CC) -x $(CFLAGS) $< -o $#
#Create assembler file of a C source
%.s: %.c
$(CC) -S $(CFLAGS) $< -o $#
#Cleans all generated files
clean:
rm -f $(OBJ_FILES)
rm -f $(OUTPUT).elf
rm -f $(OUTPUT).hex
rm -f $(OUTPUT).map
Edit: I'm away from my computer now so I can't check this but thinking about my issue I'm starting to think I don't have a file named main.c in that directory. Even if I did I still think the makefile would not work correctly because I don't fully understand rules in makefiles.
My error was coming from the fact that I did not have a main.c file in my directory. Make sure you backup files when you're messing with the OBJ_FILES or similar variable and have a line that will delete whatever is in that variable upon a make clean.
As for the rules, I had to make one small fix to achieve what I wanted. I changed
$(OUTPUT).elf: $(PROCESS_FILES)
$(CC) $(CFLAGS) $(OBJ_FILES) -o $(OUTPUT).elf -Wl,-Map,$(OUTPUT).map
to
$(OUTPUT).elf: $(OBJ_FILES)
$(CC) $(CFLAGS) $(OBJ_FILES) -o $(OUTPUT).elf -Wl,-Map,$(OUTPUT).map
This then sees it needs the object files which in turn needs the preprocessed files.
Edit: I also changed OBJ_FILES=$(PROCESS_FILES:.e=.o) to OBJ_FILES=$(SRC_FILES:.c=.o). I also added $(PROCESS_FILES) to $(OUTPUT).elf: $(OBJ_FILES) so the rule would generate both the preprocessed files and object files independently. I had to change $(OBJ_FILES): %.o : %.e to $(OBJ_FILES): %.o : %.c to make this work.
I have many file with extension .cpp
f001.cpp
abc.cpp
...
I try compile any file with this
%.cpp:
g++ -o $* $*.cpp
but I get
make: *** No hay objetivos. Alto.
Does this work?
f001.o:
%.o: %.cpp
g++ -o $# $<
EDIT:
Good! Now try this:
OBJETIVOS = f001.o abc.o def.o ghi.o
todos: $(OBJETIVOS)
%.o: %.cpp
g++ -o $# $<
There is one problem here. Usually abc is the executable binary file, and abc.o is the object file. You are building executable files, but calling them abc.o. If you want them to be executable files, it would be better to call them abc.
with the answer of #Beta, I solved with
files = $(basename $(shell ls *cpp))
all: $(files)
%: %.cpp
g++ -o $# $<
clean:
rm $(files)
https://gist.github.com/3726212
I need to embed several text files in a binary. It's currently done with two lines added in configure.in script that do "clean" and perform objcopy to the $target.o files. Don't ask WHY it's required, in this app, it just is.
What I want to do is write some automake (Makefile.am) difinitions that would list those text files as source and tell make to objcopy them into *.o files I need to link with the final target. I could also add them to CLEANFILES, which I want.
Now, I know I say final_LDADD, but I can't find the way to tell automake/configure to do that trick.
Help...
Something like:
libxxx.a : text1.o text2.o
$(AR) cru $# $^
text1.o : text1.txt
$(OBJCOPY) $< $#
text2.o : text2.txt
$(OBJCOPY) $< $#
...
final_LDADD = libxxx.a
...
CLEANFILES += libxxx.a text1.o text2.o
Slightly modified ldav1s's solution:
object_files = file0.o file1.o file2.o ... fileN.o
all:
for SQL in $$(echo ${object_files} | sed -r 's~\.o\b~~g'); do \
$(OBJCOPY) $$SQL $$SQL.o; \
done;
CLEANFILES = ${object_files}
I'm having troubles with my Makefile :-(
I have a mix of assembly and C sourcecode that I need to link together. I need different build-instructions for those two types. Since both the assembler and C compiler output *.o files, I cannot use the general %.o:%.c construction often found in example Makefiles
This what I'm trying now:
Get a list of all C files and their resulting output files:
C_SRCFILES := $(shell find $(SRCDIRS) -type -f -name "*.c")
C_OBJFILES := $(patsub %.c,%.o,$(C_SRCFILES))
Get a list of all asm files and their resulting output files:
A_SRCFILES := $(shell find $(SRCDIRS) -type -f -name "*.asm")
A_OBJFILES := $(patsub %.asm,%.o,$(A_SRCFILES))
When I echo those vars to the screen, they seem to be correct, but how I do define my targets now?
I tried something like this
$(A_OBJFILES): ($A_SRCFILES)
$(AS) $(AFLAGS) -o $# $*
$(C_OBJFILES): ($C_SRCFILES)
$(CC) $(CFLAGS) -c -o $# $*
all: $(A_OBJFILES) $(C_OBJFILES)
$(LD) $(LDFLAGS) $(A_OBJFILES) $(C_OBJFILES) -o $(TARGET_OUTPUT)
but ofcourse, this doesn't work...
Any suggestions?
First problem: a misplaced parenthesis or two.
$(A_OBJFILES): ($A_SRCFILES)
Notice that you have the $ inside the ( in ($A_SRCFILES). Make expands $A, which is nothing, and things go downhill. I think you meant $(A_SRCFILES), and the same thing in the other rule.
Second problem: I don't know the syntax of the assembler, but the syntax of the compiler command is wrong:
$(CC) $(CFLAGS) -c -o $# $*
The variable $* is nothing if we're not in a pattern rule, which we're not (yet). And anyway, if we were in a pattern rule and you were trying to build foo.o, this command would look for the source file foo, and there's no such file. Do it this way:
$(CC) $(CFLAGS) -c -o $# $<
Third problem: each object file depends on all source files (in each rule). Try this instead:
$(A_OBJFILES): %.o : %.asm
...
$(C_OBJFILES): %.o : %.c
...
(Now it's a pattern rule.)
Fourth problem: a lot of redundancy in the last rule. Change it to this:
all: $(A_OBJFILES) $(C_OBJFILES)
$(LD) $(LDFLAGS) $^ -o $(TARGET_OUTPUT)
or better still:
all: $(TARGET_OUTPUT)
$(TARGET_OUTPUT): $(A_OBJFILES) $(C_OBJFILES)
$(LD) $(LDFLAGS) $^ -o $#
Since both the assembler and C compiler output *.o files, I cannot use the general %.o:%.c construction often found in example Makefiles
Sure you can:
%.o : %.c
# commands to make .o from a corresponding .c
%.o : %.asm
# commands to make .o from a corresponding .asm