I have a very simple operator problem in VHDL. I try to compare some inputs with logical operators but get an error message...
entity test is
port (
paddr : in std_logic_vector(15 downto 0);
psel : in std_logic;
penable : in std_logic;
pwrite : in std_logic
);
end entity test;
signal wrfifo_full : std_logic;
process (paddr, psel, penable, pwrite, wrfifo_full) is
begin
if (((paddr(8 downto 2) = "1000000")) and (psel and penable) and (pwrite and not(wrfifo_full))) then
dt_fifo_wr_i <= '1';
else
dt_fifo_wr_i <= '0';
end if;
end process;
Unfortuantely, I get then the following error message:
if (((paddr(8 downto 2) = "1000000")) and (psel and penable) and
(pwrite and not(wrfifo_full))) then
| ncvhdl_p: *E,OPTYMM (hdl/vhdl/test.vhd,523|43): operator argument type mismatch
87[4.3.3.2] 93[4.3.2.2] [7.2]
Anyway sees the problem?
Cheers
psel, penable, pwrite and wrfifo_full are all std_logic.
In vhdl, to write the test they way you have, they would need to be boolean.
Instead write the code so that you are comparing their values to 1 or zero.
(paddr(8 downto 2) = "1000000" and
psel = '1' and penable ='1' and
pwrite = '1' and wrfifo_full = '0')
As George said, you have to currently convert all your std logics to booleans.
In VHDL-2008 however, there is a new conditional operator (??) which is applied implicitly to statements such as yours, which means they will work as you hoped. You'll have to enable VHDL-2008 support on you compiler (or whinge at your supplier to get with the times :)
This book is a good read on all the new bits that VHDL2008 gives us:
VHDL-2008 Just the new stuff
Section 4.4 covers the conditional operator
Related
I'm developing a simple buffering system in VHDL. I get the error I mentioned in the title for "empty" whenever I try to compile. I don't know why it won't let me invert a std_logic type. I've also been getting errors about the comparisons. For some reason, it doesn't recognize the ">" and "<" operators on status_as_int and the thresholds.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
ENTITY Buffer_Controller is
port (
empty : in std_logic;
full : in std_logic;
filling_status : in std_logic_vector(14 downto 0);
read_thresh : in integer;
write_thresh : in integer;
read_now : out std_logic;
write_now : out std_logic
);
END ENTITY;
ARCHITECTURE ctrl of Buffer_Controller is
signal status_as_int : integer;
BEGIN
status_as_int <= to_integer(unsigned(filling_status));
read_now <= '1' when (NOT(empty) AND status_as_int > read_thresh) else
'0';
write_now <= '1' when (NOT(full) AND status_as_int < write_thresh) else
'0';
END ARCHITECTURE;
empty and full are not booleans. They're std_logic, which is a user defined type (defined in the ieee.std_logic_1164 library). That's not a boolean.
Yes, you can invert them, but the result will still be std_logic. (The overloaded implementation of NOT for std_logic is also defined in the ieee.std_logic_1164 library).
To convert to boolean, You need to compare them to something that can be interpreted as std_logic, e.g.
read_now <= '1' when
empty = '0' AND
status_as_int > read_thresh
else '0';
I am trying to verify a design written in VHDL using SystemVerilog's assertions. however I got a problem when I have a non defined signal'X'
Just for example here is a code of a Comparator:
entity FP_comparator_V2 is
port (
comp_in1 : in std_logic_vector(31 downto 0);
comp_in2 : in std_logic_vector(31 downto 0);
less : out std_logic;
equal : out std_logic;
greater : out std_logic
);
end FP_comparator_V2;
architecture behav of FP_comparator_V2 is
-- signal, component etc. declarations
begin
-- architecture body
process(comp_in1, comp_in2)
begin
if comp_in1 = comp_in2 then
equal <= '1';
less <= '0';
greater <= '0';
else
equal <= '0';
...
end if;
end process;
end behav;
and the assertions
property FP_Comparator_V2_1_1;
#(posedge `assertion_check_clk29M4912 or negedge `assertion_check_clk29M4912)
(fp_comp_intf.Comp_in1 === fp_comp_intf.Comp_in2) |-> (fp_comp_intf.equal);
endproperty
DS_3_4_69_1_1:
assert property(FP_Comparator_V2_1_1);
cover property(FP_Comparator_V2_1_1);
property FP_Comparator_V2_1_2;
#(posedge `assertion_check_clk29M4912 or negedge `assertion_check_clk29M4912)
(fp_comp_intf.Comp_in1 !== fp_comp_intf.Comp_in2) |-> (!fp_comp_intf.equal);
endproperty
DS_3_4_69_1_2:
assert property(FP_Comparator_V2_1_2);
cover property(FP_Comparator_V2_1_2);
When Comp_int1 and Comp_int2 have defined values the simulation works fine if one of them have a undefined value also works fine but when both signals have undefined value it gives error For example :
Comp_int1= 48xx_xxxx; Comp_int2=47xx_xxxx ==>Equal = 1
I suppose it compares bit by bit so Equal should be '0' Please if you know a book or a website explaining the behavior of signals after synthesis or the logic behind undefined signals I would be thankful if you put it in a comment
thank you
I would suggest eliminating undefined values for signals in the design first. You can do this by initializing values to those signals in all possible cases. This helps in eliminating the X-propagation in the design.
I've some problem with my synthesis tool. I'm writing a module and I'm tryng to make it parametric and scalable. In my design I've a FSM and some counters. The counters have a parametric width ( they are function of the width of the datapath ). The problem is that I'm using that counter to drive a case statements. The synthesizer gives me back this error :
2049990 ERROR - (VHDL-1544) array type case expression must be of a locally static subtype
I've also tried to use subtype, but it doesnt work. The declaration is :
constant LENGTH_COUNTER_WORD : integer := integer(ceil(log2(real(WIDTH_DATA/WIDTH_WORD))));
subtype type_counter_word is std_logic_vector( LENGTH_COUNTER_WORD - 1 downto 0);
signal counter_word : std_logic_vector( LENGTH_COUNTER_WORD - 1 downto 0);
The case :
case type_counter_word'(counter_word) is
when (others => '1') =>
do_stuff();
when others =>
do_other_stuff();
end case;
I cannot switch to VHDL-2008. I've read I can use variable, but I'd like to find a different solution, if it exists. I cannot imagine there isn't any way to give parameters to synthesizer before the synthesis.
This is fixed in VHDL-2008. You can only work around it in earlier standards by using cascaded if statements (with the attendant priority logic). Variables don't make a difference when determining if choices are locally static.
I'm not sure how complicated your do_stuff() and do_other_stuff() operations are, but if you are just doing simple signal assignments, you could look into the and_reduce() function in the ieee.std_logic_misc library.
As an example:
output <= '1' when and_reduce(type_counter_word'(counter_word)) = '1' else '0';
Otherwise, as Kevin's answer suggests, a process block using if statements might be your best option.
About the time of Kevin's good enough answer, I had written this to demonstrate:
library ieee;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
entity counterword is
generic (
WIDTH_DATA: positive := 16;
WIDTH_WORD: positive := 8
);
end entity;
architecture foo of counterword is
constant LENGTH_COUNTER_WORD : integer :=
integer(ceil(log2(real(WIDTH_DATA/WIDTH_WORD))));
subtype type_counter_word is
std_logic_vector( LENGTH_COUNTER_WORD - 1 downto 0);
signal counter_word : std_logic_vector( LENGTH_COUNTER_WORD - 1 downto 0);
procedure do_stuff is
begin
end;
procedure do_other_stuff is
begin
end;
begin
UNLABELLED:
process (counter_word)
begin
-- case type_counter_word'(counter_word) is
-- when (others => '1') =>
-- do_stuff;
-- when others =>
-- do_other_stuff;
-- end case;
if counter_word = type_counter_word'(others => '1') then
do_stuff;
else
do_other_stuff;
end if;
end process;
end architecture;
Note because type_counter_word is a subtype you can provide the subtype constraints in a qualified expression for the aggregate:
if counter_word = type_counter_word'(others => '1') then
From IEEE Std 1076-2008:
9.3.5 Qualified expressions
A qualified expression is a basic operation (see 5.1) that is used to explicitly state the type, and possibly the subtype, of an operand that is an expression or an aggregate.
This example analyzes, elaborates and simulates while doing nothing in particular. It'll call the sequential procedure statement do_other_stuff, which does nothing.
(For do_stuff and do_other stuff, empty interface lists aren't allowed).
I am currently in the middle of a project where I am attempting to design a single cycle cpu. I am doing this without any pipe-lining, since that would greatly add to the complexity of the design. I am simply taking baby steps as I learn this. I find myself stuck at this portion where I am simply attempting to code a Program Counter(PC) using previously made components.
The model of my design looks like this picture here. Sorry, no idea why it came out dark, but if you click on it it shows correctly. The PC and theMUX are both 32 bit components, so I assume the adder is as well.
Here is the code I have been given, my implementation begins at the begin statement on line 41.
Pay no attention to it for now, its just a bunch of random gibberish I was attempting.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
---------------------------------------------------
entity pc_update is
port( clk: in std_logic; -- clock
incH_ldL: in std_logic; -- increment PC = PC + 4 when high,
-- load PCInput when low
PCInput: in std_logic_vector(31 downto 0); -- external input for PC
InstrAddr: out std_logic_vector(31 downto 0) ); -- instruction address
end entity pc_update;
----------------------------------------------------
architecture pc_update_arch of pc_update is
component register32 is
port( clr: in std_logic; -- async. clear
clk: in std_logic; -- clock
ld: in std_logic; -- load
D: in std_logic_vector(31 downto 0); -- data input
Q: out std_logic_vector(31 downto 0) ); -- data output
end component register32;
component mux2to1_32 is
port( sel: in std_logic; -- selection bit input
X0: in std_logic_vector(31 downto 0); -- first input
X1: in std_logic_vector(31 downto 0); -- second input
Y: out std_logic_vector(31 downto 0)); -- output
end component mux2to1_32;
signal PC_current: std_logic_vector(31 downto 0); -- the current state of PC reg
signal PC_add_4: std_logic_vector(31 downto 0); -- output from the adder
signal PC_next: std_logic_vector(31 downto 0); -- output from the MUX
begin
PC: register32 Port Map(
clk, Q, clr, D);
MUX: mux2to1_32 Port Map(
X0,sel,X1,Y);
process (incH_ldL)
begin
wait until (clk = '1');
if incH_1dL = '0' then
InstrAddr <= X0;
else InstrAddr <= X1;
end if;
end process;
end architecture pc_update_arch;
I am fairly new to this so I have only a faint idea of how signals work, and no idea how I am supposed to implement the components into the design. I am also confused that I wasnt asked to build the adder ahead of time. Is it now necessary to use it as a component im guessing?
Anyhow, I have attempted different things that stumbled upon searching, such as the port mapping you see. But I always get some sort of error, currently the error im receiving is that objects Q, clr, and D are used but not declared. How do I declare them?
If I get rid of those statements, the error simply repeats for objects X0, X1, and Y.
Any help in the right direction would be greatly appreciated. Thanks guys!
Also, just in case you need them,
The register
library ieee ;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
---------------------------------------------------
entity register32 is port(
clr: in std_logic; -- async. clear
clk: in std_logic; -- clock
ld: in std_logic; -- load
D: in std_logic_vector(31 downto 0); -- data input
Q: out std_logic_vector(31 downto 0) ); -- data output
end entity register32;
----------------------------------------------------
architecture register32_arch of register32 is
begin
process(clk, clr)
begin
if clr = '1' then
q <= x"00000000";
elsif rising_edge(clk) then
if ld = '1' then
q <= d;
end if;
end if;
end process;
END register32_arch;
and the MUX
library ieee ;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
---------------------------------------------------
entity mux2to1_32 is
port( sel: in std_logic; -- selection bit input
X0: in std_logic_vector(31 downto 0); -- first input
X1: in std_logic_vector(31 downto 0); -- second input
Y: out std_logic_vector(31 downto 0)); -- output
end entity mux2to1_32;
----------------------------------------------------
architecture mux2to1_32_arch of mux2to1_32 is
begin
Y <= X1 when (SEL = '1') else X0;
end architecture mux2to1_32_arch;
EDIT
Ok, NO idea if I did this correctly, but I rewrote the portmaps. I was having errors of port names (sel, clk, X0, X1..etc) being "used but not initialized. So that is why clr, clk and ld have initial values. Once again, no idea if that is correct, but it made the errors go away. I also realized I never added the register32 and mux2to1_32 VHDL files to my project, and after doing so got rid of the other errors I was having.
So as stands, the code compiles, I have included in the project a VWF simulation file for testing, but I KNOW the results are gonna be incorrect.
I dont know everything that is wrong yet, but I know I need to do something with PC_add_4. THis value needs to basically be (PC_current + 4), but Im not sure how to do this.
Here is the updated portion of code(everything else is the same)
PC: register32 Port Map(
clr => '0',
clk => '0',
ld => '1',
Q => PC_current,
D => PC_next
);
MUX: mux2to1_32 Port Map(
sel => incH_ldL,
X0 => PCInput ,
X1 => PC_add_4,
Y => PC_next
);
process (incH_ldL)
begin
if (rising_edge(clk)) then
if incH_ldL = '0' then
InstrAddr <= PC_current;
else InstrAddr <= PC_add_4;
end if;
end if;
end process;
And, in case they help, my list of errors..im guessing the pin related errors are because I dont have any hardware assignments made yet.
Warning (10541): VHDL Signal Declaration warning at pc_update.vhd(38): used implicit default value for signal "PC_add_4" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations.
Warning (10492): VHDL Process Statement warning at pc_update.vhd(61): signal "clk" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning: Output pins are stuck at VCC or GND
Warning: Design contains 34 input pin(s) that do not drive logic
Warning: Found 32 output pins without output pin load capacitance assignment
Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'.
Warning: Can't generate programming files because you are currently using the Quartus II software in Evaluation Mode
Warning: No paths found for timing analysis
Critical Warning: No exact pin location assignment(s) for 66 pins of 66 total pins
SECOND EDIT
So yeah I fixed up my code by adding
PC_add_4 <= (PC_current + 4 );
after the port mappings, and adding "clk" to the process sensitivity list.
However my waveforms in my simulation are still wrong I believe, as shown here.
It appears to be treating incH_lDL as a clear signal, rather than simply passing PCInput to InstrAddr. This is most likely due to my setting of it to a default '0' in the port map. I did this earlier because it was giving me "used but not declared" errors. Ill try messing with it and post my findings.
Third EDIT
I have edited my code as such:
process (incH_ldL, clk)
begin
if rising_edge(clk) then
if (incH_ldL = '0') then
InstrAddr <= PCInput ;
else InstrAddr <= PC_add_4;
end if;
end if;
end process;
My simulation now shows that when incH_lDL = 0, PCInput is loaded into InstrAddr, however, when incH_lDL = 1, it simply loads the value '4', and doesnt increment at the start of every clock cycle like its supposed to...I need to make use of PC_current, but I am not sure how....sicne you cant assign one signal to another like "PC_current <= PCInput". I will try some more things,in the mean time, any pointers would be greatly appreciated.
FOURTH EDIT
THanks to anyone still reading this, and bearing through all the reading.
I have attempted to use PC_next and PC_current in my implementation, but have run into "multiple constant drivers for net "PC_next" errors.
MY process code:
process (incH_ldL, clk, PC_next, PC_current)
begin
if rising_edge(clk) then
if (incH_ldL = '0') then
PC_next <= PCInput;
else PC_next <= PC_add_4;
end if;
end if;
InstrAddr <= PC_current;
end process;
I am aware that this error comes when these assignments are made within loops? I am truly at a loss here at what to try next.
Your port maps in the first code need to be ported to signals. You are placing the port names of the components in the port map, which is incorrect. What you would like to do is create signals that can connect those components, and place them in the port map fields instead (to match the connections in your image).
I am writing a VHDL process that needs to compare an input value to zero. The input may contain metavalues ('U', 'X', 'L', 'H', etc.), in which case zero should not be asserted.
Unfortunately, ModelSim issues a warning with each comparison:
# ** Warning: NUMERIC_STD."=": metavalue detected, returning FALSE
# Time: 14 ns Iteration: 1 Instance: /tb/uut
Any ideas on how to code the below in order to avoid such warnings? Turning off numeric_std warnings globally is not an option.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity Test is
port (
clk : in std_logic;
reset : in std_logic;
i_in_data : in unsigned(31 downto 0);
o_out_zero : out std_logic
);
end Test;
architecture rtl of Test is
begin
process(clk, reset) begin
if(reset='1') then
o_out_zero <= '0';
elsif(rising_edge(clk)) then
if(i_in_data = (i_in_data'range=>'0')) then
o_out_zero <= '1';
else
o_out_zero <= '0';
end if;
end if;
end process;
end architecture;
If the output of o_out_zero doesn't matter in the presence of metavalues, then the useful function to_01 from numeric_std can be used to eliminate them in the comparison expression. See also to_01xz etc for similar purposes...
Replace
if(i_in_data = (i_in_data'range=>'0')) then
with
if to_01(i_in_data) = (i_in_data'range=>'0') then
and it should be good.
You do know that parentheses around the boolean expressions in an if-statement are unnecessary, right? The less VHDL looks like C, the better...