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Why the memory of the USB devices is always in the powers of 2?
Because all memory devices are essentially an array of bytes or words. As such there is an address (index) and data which are both binary numbers. So a 1 Megabyte memory will have a 20 bit address "bus" and an 8 bit data bus. These buses are physically constructed with one electrical conductor per bit, so the 1Meg device will have 20 address pins and 8 data pins. In DRAM, there may be multiplexing, where half of the address is sent on one clock cycle and the other half on another clock cycle - this can reduce the number of physical pins and traces on a circuit board. Making a 2Meg memory out of such chips is easy, you connect the address and data pins together and then use the "chip select" pin to determine which one is being accessed via the 21st address bit. Partitioning memory in a non-power-of-2 scheme requires a LOT more circuitry and interconnection complexity to figure out which chip your data is in, and it means not using every bit combination of the address lines which all mean less efficient use of circuitry.
Hope that helps.
Because flash memory chips are always manufactured with capacities in powers of two, as it doesn't waste address space. Because addressing is done in binary, the maximum number is always a power of two (minus 1).
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I'm about to build a desktop computer and I'm trying to understand how are this PCIe lanes distributed. The goal is being able to calculate how many lanes do I need for a certain setup. I'm looking at the Asus Z170-P motherboard, which according the specifications [1]:
It contains the Z170 chipset.
You can read on the board that it is "CrossfireX Ready" which I believe implies you could plug in 2 graphic cards.
The specs say it has two PCIe x16 slots, one that works at x16 mode and another one that only works at x4 mode.
First, according to the Z170 chipset specifications, it supports up to 20 PCIe lanes. However, there is no single processor that fits into the LGA1151 socket with support for 20 or more PCIe lanes [2]. Why have a chipset with support for 20 lanes when the processor will only be able to handle up to 16?
Second, supported PCIe port configurations by the chipset are "1x16, 2x8, 1x8+2x4". If I were to plug in two graphic cards, would they both work at x4 mode or x8/x4 modes? Shouldn't a motherboard designed for using two graphic cards be able to handle 32+ PCIe lanes so both graphic cards work at x16 mode?
The (up to) 20 PCIe lanes from the Z170 are in addition to the 16 lanes that come directly out of the CPU.
I don't see any reason that it wouldn't run one graphics card at 16x and one at 4x. But it does seem odd to me that they call it "Crossfire-ready" without 2 x16 slots.
More info on the Z170 here:
http://www.tomshardware.com/reviews/skylake-intel-core-i7-6700k-core-i5-6600k,4252-2.html
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A PC has a microprocessor which processes 16 instructions per microsecond. Each instruction is 64 bits long. Its memory can retrieve or store
data/instructions at a rate of 32 bits per microsecond.
Mention 3 options to upgrade system performance. Which option gives most improved performance?
And the answer provided is
a) upgrade processor to one with twice the speed
b) upgrade memory with one twice the speed
c) double clock speed
(b) gives most improved performance.
Overcoming the bottleneck of a PC can improve the integrated performance.
However, my problem is that I am not sure of why b gives the most improved performance. Additionally, would a and c give the same performance? Will it provide the same performance? Can it be calculated? I am not sure of how these different parts would work on the performance.
Your question's leading paragraph contains the necessary numbers to see why it's b):
The CPU's processing rate is fixed at 16 instructions per microsecond. So an instruction takes less than a microsecond to execute.
Each instruction is 64 bits long, but the memory system retrieves data at 32 bits per microsecond. So it takes two microseconds to retrieve a single instruction (i.e. 64 bits).
The bottleneck is clear: it takes longer to retrieve an instruction (2μs) than it does to execute it (1/16thμs).
If you increase the CPU speed (answer a)), the CPU will execute an individual instruction faster, but it will still be waiting idle at least 2μs for the next instruction to arrive, so the improvement is wasted.
To eliminate bottlenecks you need to increase the memory-system's speed to match the CPU's execution speed, so the memory needs to read 64 bits in a 1/16μs (or 32 bits in 1/32μs).
I assume answer c) refers to increasing the speed of some systemwide master clock which would also increase the CPU and Memory data-rates. This would improve performance, but the CPU would still be slaved to the memory speed.
Note that your question describes a simplistic computer. Computers were like this originally, where the CPU accessed memory directly, instruction-by-instruction. However as CPUs got faster, memory did not - so computer-engineers added cache levels: this is much faster memory (but much smaller in capacity) where instructions (and data memory) can be read as fast as a CPU can execute them, solving the bottleneck without needing to make all system memory match the CPU's speed.
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I am currently volunteering to learn about linux servers and also I am interested in learning about cluster computing techniques.
In this lab, they have a small cluster with one head node and two compute nodes.
When I tried the lscpu command on head node, compute node1,node2. Click the link to view the details.
CPUs - 24 in head, computenode1 and computenode2. Is it referring to 24 physical CPUs in the motherboard?
Sockets - 2 in head, computenode1 and computenode2.Can anyone explain it?
Cores per socket - 6 in head, computenode1 and computenode2.Can anyone explain it?
Threads per core - 2 in head, computenode1 and computenode2.Can anyone explain it?
A socket is the physical socket where the physical CPU capsules are placed. A normal PC only have one socket.
Cores are the number of CPU-cores per CPU capsule. A modern standard CPU for a standard PC usually have two or four cores.
And some CPUs can run more than one parallel thread per CPU-core. Intel (the most common CPU manufacturer for standard PCs) have either one or two threads per core depending on CPU model.
If you multiply the number of socket, cores and threads, i.e. 2*6*2, then you get the number of "CPUs": 24. These aren't real CPUs, but the number of possible parallel threads of execution your system can do.
Just the fact that you have 6 cores is a sign you have a high-end workstation or server computer. The fact that you have two sockets makes it a very high-end computer. Usually not even high-end workstations have that these days, only servers.
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I have the following case, where a CPU with 16bit (d0-d15) data line and i want to connect it to a 8bit (d0-d7) data line of a RAM for read and write. I can connect the first d0-d7 to each other, but the CPU still have another d8-d15 left over, i am sure i can utilize this extra data line to read more information from the RAM than just 8bits at a time. But I am not sure how the connections would be.
Here is the diagram:
I am not sure how the RAM would looks if i connect the extra d8-d15 lines to RAM? do i connect using a multiplexer to decide when to select the data from which 8bit line?
If the CPU asks for 16 bits, then the RAM needs to accept and deliver 16 bits in parallel, so you'd need logic to create a second RAM access. For a simple design, that is not worthwhile.
Your options are:
Use 16 bit RAM.
Use two 8 bit RAMs in parallel.
Find out if the CPU can be instructed to generate two 8 bit accesses for every 16 bit access.
If the CPU has an A0 address line, there is actually a chance that it does support generating 8 bit wide accesses, as you wouldn't need it if all accesses are on word boundaries anyway.
Note that this will be slower than just using 16 bit accesses.
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What is dominate factor of the disk price, capacity or IOPS? I think the answer of this question should also answer this one in which i asked why cost of disc I/O per access is PricePerDiskDrive/AccessesPerSecondPerDisk.
Thanks
Chang
The factor dominating the price is the market segment: Home disks are cheapest, server disks most expensive.
It depends on several factors, as stated in the previous answer, you have the segment, home or business.
Then there is the architecture:
SCSI (bus controller with high speeds)
SSD (flash)
SATA (regular drive)
SAS (serial attached scsi, backwards compatible with SATA)
SAS and SCSI are mostly disks running at high speeds, this makes them more expensive.
SATA disks for home use at normal speeds (5400 or 7200 rpm) are expensive based on capacity and brand. If a company has the first 3 TB disk it will be very expensive, when 3 companies have those disks, prices will decrease because of competition
SSD is a technology that got affordable, but still a lot more expensive than regular SATA (with platters). This is because there are no turning parts and it uses faster memory.
Also a very nice thing to remember :
The faster the drive, the more expensive, there for it is normal that the better your IOPS are the more expensive it is.
Capacity has a price, but it is linked to the drives speed and the recent evolution in technology.