I need to get the absolute of the signal in Xilinx Simulink.
I can use a mcode block and write matlab code to achieve it. But, just curious if there is a better way of doing it.
I am very new to using Simulink(Xilinx). Is there any abs block as in Simulink in Xilinx library.
Thanks
Xilinx have the following Answer Record:
http://www.xilinx.com/support/answers/10975.htm
which pretty much covers what you've already done!
Related
A snippet of my task is to generate, let's say, 256 quasi-random numbers using CUDA. I've read cuRAND docs and from there I've learnt that I need to use a set of direction vectors, which I can get using curandGetDirectionVectors32 function. But the problem is that I still can not understand what is 'set of direction vectors'. Especially how to use it, how to limit its length etc.
Also there's no example in Device API Examples with Sobol's generator. And there's no working example in google. I've found some explanation but scrambled_sobol_v_host is not declared in that scope and unclear for me.
So, my question is could anyone, please, provide me with tiny working example of usage of this generator?
And I have troubles with understanding difference between Sobol's generator and scrambled Sobol's generator.
Thank you in advance.
Direction vectors are the seeding method for that number generator. For implementation you should be able to follow using QuasirandomGenerator (for dummies)
We are using a tool to convert the code into RTL.
Using those VHDL files, we would like to synthesis the code using FPGA.
In the synthesis results, we see the following table:
Slice Logic Utilization Used Available Utilization
Number of DSP48E1s 15 864 1%
I would like to search in VHDL files to see which operations use these units.
Is there any way to find them? or any documentation which shows the operations causing DSPs to be used?
There are a few ways that a DSP48 may be used in your VHDL.
It may be inferred. This is when the synthesis tool is smart by looking at an operation that you are doing (such as a multiply) and realizing that it would be most efficient to do the multiply with a dedicated resource (DSP48) instead of fabric/logic.
It may be instantiated. This means that the primitive was directly called out in your source file. The designer said that I know I want to use this piece of hardware, so I am going to call it out explicitly. This is when you could do a text search for "DSP48" in your VHDL source files.
It may be part of a core. If it is part of a core, you may or may not have visibility into that core. For example, how the core is actually implemented may be different than the behavioral model which is used for simulation.
In any case, as recommended by Russell, using Xilinx toolset to determine utilization of primitives in the design hierarchy can be a good first pass to figuring out where the units are coming from. Additionally, you can always open up FPGA Editor, see what the DSP48 units are called and what signals are going to/out of the DSP48 for additional hints on where it is in your design.
It sounds like you're trying to find your Module Level Utilization. I know that Xilinx ISE supports this. Under Design Overview there's an option called Module Level Utilization that breaks down every module in your VHDL design and tells you where the Regs, LUTs, BRAMs, and DSPs are used.
If you're unable to find it, look for any large multiplications in your design. Large multiply/accumulate operations will synthesize into DSP48s.
Sorry for such a general question. I have experience in Verilog but new to FPGA and Quartus II. I use Quartus II to try to compile a design and to see how much logic the design uses. I followed the quick tutorial of Quartus II by Altera. http://www.altera.com/literature/manual/mnl_qts_quick_start.pdf
However, after the step of analysis and synthesis, I noticed there is no logic utilization at all. Only the two Input pins of top module could be seen.
The top module of my design is
RiSC(clk,reset)
Naturally, after compilation, there is still nothing but two pins.
Have you ever met this problem? Could you give me some hint? The design contains hundreds of lines of verilog codes so there should be logic utilization.
Thanks!
Unused outputs will be optimized out. You're going to have to route out some outputs otherwise the synthesizer will nuke all of the logic.
I designed a circuit using RTL SystemC library. This circuit works fine and I can simulate it properly. Now I want to deploy it into an FPGA and I'm looking for a way to convert my SystemC code into VHDL or Verilog in order to use it in Xilinx ISE.
Is there a way to do that ? Or do O have to do all the programming again but this time, in VHDL ?
Probably yes, you have to clone the existing design in VHDL - certainly, if you must use ISE. But it might be worth looking at Vivado first.
However, assuming your simulator understands VHDL as well as SystemC, this will be straightforward because you can drop the VHDL into the existing testbenches and verify its correct function, thereby reusing at least half of your proglamming so far.
And presumably you can use the SystemC version as an accurate specification; translating this into VHDL should be quite a straightforward process.
I have pex_pkg.vhd and I want to use this library to make floating point adder but altera max+plus II give me an error can't open "PEX_lib" how to include this library in max+plus ?
I'd stay away from Max plus II if I were you, it's v. old - its VHDL support was always spotty, and IIRC using libraries other than work wasn't possible.
Altera's tool is Quartus now - I'm sure that can handle multiple libraries.
You should check out David Bishop's VHDL Floating Point Library. This is by the same author who wrote the VHDL floating point libraries that are build into VHDL 2008, but these are usable with older and more common VHDL tools. They are fully tested and synthesizable. The only potential downside is that because they are implemented via functions, they can only describe the common case of either pipelined or combinational data paths. (If you want, for instance, a smaller multi-cycle digit-serial design, you have to resort to a different library.)
Are you sure you wish that? Most floating point libraries aren't synthesizable.