Makefile prerequisite variable evaluation - makefile

Question

I have a large project with multiple Makefiles, and I need to modify the order in which projects are built. However, I cannot seem to understand when variables that are prerequisites get evaluated. Everything that I've read seems to indicate that the entire Makefile is parsed before the dependency graph is built, so I don't understand why this sample is not working:
OBJECTS=main.o
EXE_NAME=test.exe
$(EXE_NAME): $(OBJECTS)
#echo PREREQUISITES: $^
#echo OBJECTS: $(OBJECTS)
$(CXX) $(CXXFLAGS) $(OBJECTS) -o $#
#include shape.mk
#----VV---Contents of shape.mk---VV----
OBJECTS+=Shape.o
OBJECTS+=Square.o
Shape.o: Shape.hpp
Square.o: Shape.hpp Square.hpp
#----^^----End of shape.mk-------^^----
main.o: Square.hpp
.PHONY: clean
clean:
-rm -fr $(OBJECTS) $(EXE_NAME)
When I run this Makefile, however, I get:
PREREQUISITES: main.o
OBJECTS: main.o Shape.o Square.o
g++ main.o Shape.o Square.o -o test.exe
g++: Shape.o: No such file or directory
g++: Square.o: No such file or directory
make: *** [test.exe] Error 1
Why does OBJECT not have the proper value when the dependency graph is built?

Answer 1

Yes, the entire Makefile is parsed before the dependency graph is built, but the the rules and definitions are read in order. You define the test.exe rule as
test.exe: main.o
...
You then go on to redefine OBJECTS, but you've already committed to that rule, so that's what Make will use to build the graph.
Try this:
$(EXE_NAME): # This will be first, the default target.
include shape.mk
$(EXE_NAME): $(OBJECTS)
...