Makefile ifeq logical or - makefile

How do you perform a logical OR using make's ifeq operator?
e.g., I have (simplified):
ifeq ($(GCC_MINOR), 4)
CFLAGS += -fno-strict-overflow
endif
ifeq ($(GCC_MINOR), 5)
CFLAGS += -fno-strict-overflow
endif
but would like to consolidate these lines.
(yes, yes, autotools, configure, etc etc; too heavy-handed for the current situation, would like to keep everything within the Makefile here)
[logical opposite of this question: How to Use of Multiple condition in 'ifeq' statement ]

As found on the mailing list archive,
http://osdir.com/ml/gnu.make.windows/2004-03/msg00063.html
http://osdir.com/ml/gnu.make.general/2005-10/msg00064.html
one can use the filter function.
For example
ifeq ($(GCC_MINOR),$(filter $(GCC_MINOR),4 5))
filter X, A B will return those of A,B that are equal to X.
Note, while this is not relevant in the above example, this is a XOR operation. I.e. if you instead have something like:
ifeq (4, $(filter 4, $(VAR1) $(VAR2)))
And then do e.g. make VAR1=4 VAR2=4, the filter will return 4 4, which is not equal to 4.
A variation that performs an OR operation instead is:
ifneq (,$(filter $(GCC_MINOR),4 5))
where a negative comparison against an empty string is used instead (filter will return en empty string if GCC_MINOR doesn't match the arguments). Using the VAR1/VAR2 example it would look like this:
ifneq (, $(filter 4, $(VAR1) $(VAR2)))
The downside to those methods is that you have to be sure that these arguments will always be single words. For example, if VAR1 is 4 foo, the filter result is still 4, and the ifneq expression is still true. If VAR1 is 4 5, the filter result is 4 5 and the ifneq expression is true.
One easy alternative is to just put the same operation in both the ifeq and else ifeq branch, e.g. like this:
ifeq ($(GCC_MINOR),4)
#echo Supported version
else ifeq ($(GCC_MINOR),5)
#echo Supported version
else
#echo Unsupported version
endif

You can introduce another variable. It doesnt consolidate both checks, but it at least avoids having to put the body in twice:
do_it =
ifeq ($(GCC_MINOR), 4)
do_it = yes
endif
ifeq ($(GCC_MINOR), 5)
do_it = yes
endif
ifdef do_it
CFLAGS += -fno-strict-overflow
endif

I don't think there's a concise, sensible way to do that, but there are verbose, sensible ways (such as Foo Bah's) and concise, pathological ways, such as
ifneq (,$(findstring $(GCC_MINOR),4-5))
CFLAGS += -fno-strict-overflow
endif
(which will execute the command provided that the string $(GCC_MINOR) appears inside the string 4-5).

Here more flexible variant: it uses external shell, but allows to check for arbitrary conditions:
ifeq ($(shell test ".$(GCC_MINOR)" = .4 -o \
".$(GCC_MINOR)" = .5 -o \
".$(TODAY)" = .Friday && printf "true"), true)
CFLAGS += -fno-strict-overflow
endif

Note that ifeq ($(GCC_MINOR),$(filter $(GCC_MINOR),4 5)) will catch the case where GCC_MINOR is not defined at all.
If you want to catch GCC_MINOR==4 or GCC_MINOR==5 this will do trick:
ifneq ($(filter $(GCC_MINOR),4 5),)
echo "def"
endif

ifeq ($(GCC_MINOR), 4)
CFLAGS += -fno-strict-overflow
endif
ifeq ($(GCC_MINOR), 5)
CFLAGS += -fno-strict-overflow
endif
Another you can consider using in this case is:
GCC42_OR_LATER = $(shell $(CXX) -v 2>&1 | $(EGREP) -c "^gcc version (4.[2-9]|[5-9])")
# -Wstrict-overflow: http://www.airs.com/blog/archives/120
ifeq ($(GCC42_OR_LATER),1)
CFLAGS += -Wstrict-overflow
endif
I actually use the same in my code because I don't want to maintain a separate config or Configure.
But you have to use a portable, non-anemic make, like GNU make (gmake), and not Posix's make.
And it does not address the issue of logical AND and OR.

In the case that you are looking to logically "or" several boolean flags together, one practical hack can be to simply let strings concatenate: if the end result is an empty string, then none of the options were true, else non-empty then at least one of them was enabled:
# Use `docker build --pull` in case either `PULL=whatever` is set OR if the `CI` environment variable is present.
ifneq ($(PULL)$(CI),)
PULL_OR_NOT := --pull
endif
build:
docker build $(PULL_OR_NOT)

Related

Makefile: conditionals inside define

I am trying to check that variable value is yes or no, but the following always fails:
FLAG1 ?= no
FLAG2 ?= yes
define check_
ifneq ($(filter $(2),$($(1))),$($(1)))
$(error Bad $(1) argument)
endif
endef
$(call check_,FLAG1,yes no)
$(call check_,FLAG2,yes no)
What am I doing wrong?
FLAG1 ?= no
FLAG2 ?= yes
define check_
$(if $(filter $($(1)),$(2)),,$(error BAD $(1) argument))
endef
$(call check_,FLAG1,yes no)
$(call check_,FLAG2,yes no)
Notice that you added a space before FLAG1, which means $$(1) resolves to $( FLAG1), which in turn resolves to blank. The next part is that I'm not sure about is the use if ifneq inside of a define. You can use $(if ) instead
---- EDIT ------
Actually, it's a combination of the missing space and #MadScientists answer... The following also works:
define check_
ifneq ($(filter $($(1)),$(2)),$($(1)))
$$(error Bad $(1) argument [$($(1))] / [$(filter $($(1)),$(2))])
endif
endef
$(eval $(call check_,FLAG1,yes no))
Thus ifneq can be used inside of a macro... (and as #MadScientist pointed out, you have to escape the $ in front of $(error) to prevent it from being expanded by call...)
You can't use plain call with a multi-line macro. You have to use $(eval $(call ...)) if the result of the call function consists of more than one line of makefile content.
You can use this:
define check_
ifneq ($$(filter $(2),$$($(1))),$$($(1)))
$$(error Bad $(1) argument)
endif
endef
Basically, anything you want to be interpreted by the eval needs to be escaped so that call doesn't see it.

conditional execution in makefile

I have the following makefile:
C_FILE=""
cfg:
## C to CFG ####
# echo $(C_FILE)
ifndef C_FILE
$(error variable C_FILE not set)
endif
$(eval CFG_FILE := ./outputs/temp/$(shell basename $(C_FILE) .c).cfg)
gcc -fdump-tree-cfg=$(CFG_FILE) $(C_FILE)
When I run the command make cfg C_FILE="./inputs/Fib.c" it always
terminates saying variable C_FILE not set.
Lines beginning with a tab character (by default) aren't parsed by make (other than for variable expansion), they're sent directly to the shell, get rid of the indents on the lines with the make conditionals
C_FILE=""
cfg:
## C to CFG ####
# echo $(C_FILE)
ifndef C_FILE
$(error variable C_FILE not set)
endif
$(eval CFG_FILE := ./outputs/temp/$(shell basename $(C_FILE) .c).cfg)
gcc -fdump-tree-cfg=$(CFG_FILE) $(C_FILE)
I'd like to add some comments to user657267's answer.
ifndef C_FILE is always false. C_FILE is defined on the first line, or from command line. Consider using ifeq "" "$(C_FILE)".
Quote (") is normal character in makefile. Define empty variable this way:
C_FILE=
instead of using $(shell ) function, use makefile built-ins:
$(basename $(notdir $(C_FILE)))
avoid using $(eval ) if not really needed. Extract relevant code outside recipe.
My proposal is:
C_FILE=
ifeq "" "$(C_FILE)"
$(error variable C_FILE not set)
endif
CFG_FILE=./outputs/temp/$(basename $(notdir $(C_FILE))).cfg
cfg:
## C to CFG ####
# echo $(C_FILE)
gcc -fdump-tree-cfg=$(CFG_FILE) $(C_FILE)

makefile ifeq analog

I have really big sources with alot of different makefiles.
And now i need add one little condition there, where i can check if line contain what i want then i should use some symbols.
I know that ifeq must be placed at 0 column.
But I cant chage whole sources only for this condition.
How i can check what conatains in variable without ifeq?
I have something like this in define function:
$(gen_cpp_objects): $(intermediates)/%.o: \
$(intermediates)/%$(LOCAL_CPP_EXTENSION) $(yacc_cpps) \
$(proto_generated_headers) $(my_compiler_dependencies) \
$(LOCAL_ADDITIONAL_DEPENDENCIES)
$(transform-$(PRIVATE_HOST)cpp-to-o)
And i need insert condition into $(transform-$(PRIVATE_HOST)cpp-to-o)
i want something like this:
file:=somefile.someextension
define transform-cpp-to-o
#mkdir -p $(dir $#)
#echo "target $(PRIVATE_ARM_MODE) C++: $(PRIVATE_MODULE) <= $<"
ifeq ($(strip $<),$(file))
#Do something here
endif
$(hide) $(PRIVATE_CXX) \
$(addprefix -I , $(PRIVATE_C_INCLUDES)) \
You can use the if function as an inline condition:
$(if $(filter $(strip $<),$(file)), then-block, else-block)

Makefile check existence of variable from list

I have a Makefile:
#Build Configurations
CONFIGS = Debug Release Profile
#Config flags
Debug_Flags=dasd
Release_Flags=
.SECONDEXPANSION:
#Debug_safety_check Release_safety_check Profile_safety_check targets
$(addsuffix _safety_check,$(CONFIGS)):
#Check existence of variable
ifeq '$(origin $(subst safety_check,FLAGS,$#))' 'undefined'
$(error $(subst safety_check,FLAGS,$#) variable undefined)
endif
#How to make our configurations (do corresponding safety_checks)
$(CONFIGS): $$#_safety_check
This line is incorrect:
ifeq '$(origin $(subst safety_check,FLAGS,$#))' 'undefined'
I think, It is because $# expansion occurs, when calling corresponding safety check. But ifeq expansion occurs "immediately", so, in fact, we get such line:
ifeq '$(origin ' ') 'undefined'
Does some method of check variables definition from list exist?
Ufff, gotcha.
#Build Configurations
CONFIGS = Debug Release Profile
#Config flags
Debug_Flags=dasd
Release_Flags=
#Profile_Flags=
#Adds _flags suffix for each variable,
#get it's origin ('undefined' for undefined variables).
#If $(findstring) a lookup for the word 'undefined' succeeds,
#adds to the result variable
undef_flags = $(foreach c, $(CONFIGS), \
$(if $(findstring undefined, $(origin $c_Flags)), $c))
#Count words for undefined configs, must be not '0'
ifneq ($(words $(undef_flags)),0)
#strip because if flag is undefined we'll get the trash spaces
$(error Flags ($(strip $(undef_flags))) must be defined)
endif

Problem creating gnu makefile "function"

I have a big chunk of my makefile (~50 lines) that needs to be copy-pasted 5 times for different case (the different libraries used). Is it possible to create a function in a makefile and just call that function instead of copy-pasting?
This is an example of what I've tried. Basically this tries to find the right path for an installed library.
define Flags_template
$(1)_include_home := $(HOME)/usr/include
$(1)_include_home_name := $(HOME)/usr/include/$(1)
ifneq ($$(wildcard $($(1)_include_home)/$(2)),)
$(1)_Include := $$($(1)_include_home)
else
ifneq ($$(wildcard $($(1)_include_home_name)/$(2)),)
$(1)_Include := $$($(1)_include_home_name)
endif
endif
CFLAGS += -I$$($(1)_Include)
endef
$(eval $(call Flags_template,stdcout,StdCout.hpp))
.PHONY: test
test:
# stdcout_include_home_name = $(stdcout_include_home_name)
# stdcout_Include = $(stdcout_Include)
# CFLAGS: $(CFLAGS)
Typing "make", I get this output:
# stdcout_include_home_name = /home/nicolas/usr/include/stdcout
# stdcout_Include =
# CFLAGS: -I
It's so close. But note the last "-I", I always get dupplicates, one fully expended, one empty...
I don't understant what needs to be eval'ed, escaped with two $, etc.
How can I achieve this?
Thank you very much.
Does §8.8 of the GNU Make (3.82) manual help?
[...] Although it might seem overly complex to use eval in this example,
rather than just writing out the rules, consider two things: first, the template definition (in
PROGRAM_template) could need to be much more complex than it is here; and second, you
might put the complex, “generic” part of this example into another makefile, then include
it in all the individual makefiles. Now your individual makefiles are quite straightforward.
PROGRAMS = server client
server_OBJS = server.o server_priv.o server_access.o
server_LIBS = priv protocol
client_OBJS = client.o client_api.o client_mem.o
client_LIBS = protocol
# Everything after this is generic
.PHONY: all
all: $(PROGRAMS)
define PROGRAM_template =
$(1): $$($(1)_OBJS) $$($(1)_LIBS:%=-l%)
ALL_OBJS += $$($(1)_OBJS)
endef
$(foreach prog,$(PROGRAMS),$(eval $(call PROGRAM_template,$(prog))))
$(PROGRAMS):
$(LINK.o) $^ $(LDLIBS) -o $#
clean:
rm -f $(ALL_OBJS) $(PROGRAMS)
This Works (For Me)
This is the output from the GNU makefile just below:
stdcout_include_home = /work4/jleffler/usr/include
stdcout_include_home_name = /work4/jleffler/usr/include/stdcout
stdcout_Include = /work4/jleffler/usr/include
CFLAGS: -I/work4/jleffler/include -I/work4/jleffler/usr/include
GNU Makefile
CFLAGS = -I${HOME}/include
define Flags_template
$(1)_include_home := $(HOME)/usr/include
$(1)_include_home_name := $(HOME)/usr/include/$(1)
ifneq ($$(wildcard $$($(1)_include_home)/$(2)),)
$(1)_Include := $$($(1)_include_home)
else
ifneq ($$(wildcard $$($(1)_include_home_name)/$(2)),)
$(1)_Include := $$($(1)_include_home_name)
else
$(1)_Include := Neither $$($(1)_include_home) nor $$($(1)_include_home_name) contains $2
endif
endif
CFLAGS += -I$$($(1)_Include)
endef
$(eval $(call Flags_template,stdcout,StdCout.hpp))
.PHONY: test
test:
#echo stdcout_include_home = $(stdcout_include_home)
#echo stdcout_include_home_name = $(stdcout_include_home_name)
#echo stdcout_Include = $(stdcout_Include)
#echo CFLAGS: $(CFLAGS)
The difference is in the wildcard invocations:
ifneq ($$(wildcard $($(1)_include_home)/$(2)),) # Fails
ifneq ($$(wildcard $$($(1)_include_home)/$(2)),) # Works
I have half an intuition about when double-dollars and when single-dollars are needed; I am not sure I can articulate the decision, though.

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