This question already has answers here:
Make error: missing separator
(14 answers)
Closed 3 years ago.
For the following make file copied below, I am getting the missing separator error. Nothing seems to be wrong with the tabspace.
OBJS = driver.o snapshot.o
SHOBJS = malloc.o mymemory.o
CC = g++
DEBUG = -g
CFLAGS = -Wall -c $(DEBUG)
LFLAGS = -Wall $(DEBUG)
Snapshot: $(OBJS)
$(CC) $(LFLAGS) $(OBJS) -o Snapshot
driver.o: snapshot.h driver.cpp
$(CC) $(CFLAGS) driver.cpp
snapshot.o: mymemory.h snapshot.h snapshot.cpp
$(CC) $(CFLAGS) snapshot.cpp
libmymemory.so: $(SHOBJS)
gcc -shared -o libmymemory.so malloc.o mymemory.o
malloc.o: malloc.c
gcc -fPIC -g -c -Wall malloc.c
mymemory.o: mymemory.cpp
gcc -fPIC -g -c -Wall mymemory.cpp
clean:
\rm *.o *~ Snapshot
Line 18 is gcc -fPIC -g -c -Wall mymemory.cpp. Make is expecting a separator, typically :. It's not detecting this line as a command. You mistyped the intendation: you have spaces where you should have a tab.
Good editors highlight makefile lines that begin with spaces but look like they should begin with a tab instead.
I have seen this error message when a file used spaces instead of tab character(s) at the beginning of a line in the makefile.
This mostly happens if you copy paste the code from internet. Remove all the spaces from the indented lines by using the delete key. And then press the tab key, only once per line.
Save it and try running the file again. It should work now. This worked for me.
I don't know if it's accurate or an artifact of pasting the code online, but the indentation for the last two commands in the file looks like it's smaller than the commands above it. Double-check your spacing carefully.
Related
First, I should admit makefiles are something that I'm very inexperienced at, so I apologize if this is an error that I should have been able to solve myself, but I have spent several hours on this, including reading the various answers on this site, and have been unable to discover a solution.
With that said, I have created the following makefile to compile my code on a Linux machine; it completes the sub compilations just fine, but when it comes to making the output itself, xPlatST, it throws an error.
g++ -std=c+=11 -g -Wall -pthread -c -o xPlatST.o xPlatST.cpp
g++ -std=c+=11 -g -Wall -pthread -c -o stdafx.o stdafx.cpp
g++ -std=c+=11 -g -Wall -pthread -c xPlatST xPlatST.o stdafx.o -L../hwloc
g++ error: xPlatST: No such file or directory
make: *** [xPlatST] Error 1
I believe it seems to think that the xPlatST is one of it's compilation files and thus can't find it, but for the life of me I can't work out why.
hwloc is a third party library, and should be unrelated to this issue. The code compiles just fine when compiled from the command line directly.
My files are xPlatST.cpp, xPlatST.h, stdafx.cpp, stdafh.h
Code is as follows:
CXX = g++ -std=c++11
INCLUDES =
LIBS = -L../hwloc
CXXFLAGS = -Wall -g -pthread
OBJS = xPlatST.o stdafx.o
xPlatST: ${OBJS}
${CXX} ${CXXFLAGS} ${INCLUDES} -c $# ${OBJS} ${LIBS}
clean:
-rm xPlatST *.o
Any help would be greatly appreciated; thank you in advance.
Your assumption is correct. Your recipe is trying to use xPlatST as a source. Change the -c into a -o in your rule:
${CXX} ${CXXFLAGS} ${INCLUDES} -o $# ${OBJS} ${LIBS}
The -c flag tells the compiler to take all files, compile, and assemble them into an object file (.o). The -o flag specifies the destination file.
This question already has answers here:
Make error: missing separator
(14 answers)
Closed 8 years ago.
I have two .cpp files namely decryptor.cpp and prod-ent.cpp.
I have created a Makefile to for the compilation of both the files in Linux platform.
all: decryptor.cpp prod-ent.cpp
g++ prod-ent.cpp -o prod-ent -g
g++ decryptor.cpp -o decryptor -g -lcryptopp
clean:
rm prod-ent
rm decryptor
Whenever I'm trying to execute the Makefile its showing me the following error:
Makefile:2: * missing separator. Stop.
I am new to create makefiles and cannot figure out my fault. Please help me in correcting the code.
Thanks in advance !!
You need a real tab instead of space in front of g++ and rm commands. If still fails
then your editor is inserting spaces instead, even if you're hitting the tab key on your keyboard. You need to configure your editor to insert hard tabs (09 in ASCII) instead.
Like
all: decryptor.cpp prod-ent.cpp
*****g++ prod-ent.cpp -o prod-ent -g
*****g++ decryptor.cpp -o decryptor -g -lcryptopp
clean:
*****rm prod-ent
*****rm decryptor
Instead ***** replace TAB.
You can check your side by command
cat -e -t -v makefile
It's show line starting by ^I if TAB is given to that line and it end the line by $.
Also you can do by ;
all: decryptor.cpp prod-ent.cpp ; g++ prod-ent.cpp -o prod-ent -g ; g++ decryptor.cpp -o decryptor -g -lcryptopp
clean: ; rm prod-ent ; rm decryptor
when Makefile execute some tasks, il will print many information in console, can we choose to hide them? when I have many .o to generate, these information will be too many to see and they are just meaningless if we don't read them.
The following code
$(obj)environment.o: $(src)environment.c
$(CC) $(AFLAGS) -Wa, --no-warn \
-DENV_CRC=$(shell $(obj)../tools/envcrc) \
-c -o $# $(src)environment.c
will print heavy information like
arm-linux-gcc -g -Os -fno-strict-aliasing -fno-common -ffixed-r8 -msoft-float
-D__KERNEL__ -DTEXT_BASE=0x01000000
-I/home/mingzhao/Documents/bootloader/u-boot-1.2.0/include
-fno-builtin -ffreestanding -nostdinc -isystem
/home/mingzhao/Documents/bootloader/arm/4.3.2/bin/../lib/
gcc/arm-none-linux-gnueabi/4.3.2/include -pipe -DCONFIG_ARM
-D__ARM__ -march=armv4 -mabi=apcs-gnu -Wall -Wstrict-prototypes
-c -o environment.o environment.c
The "right" way to handle this (IMO) is to add this to your makefile:
$(VERBOSE).SILENT:
Then in your rules where you don't ever want the command printed (for example, an echo statement as in Beta's answer below) you prefix it with #. For all other commands, you don't prefix it with #.
What this does is enable "silent" mode by default (because the variable VERBOSE is not set and so this resolves to the .SILENT pseudo-target).
Then if you want to see everything, you add a VERBOSE=1 (actually you can set it to any non-empty value, so VERBOSE=true if you prefer). When you do that it turns off "silent" mode because the above line expands to 1.SILENT: (or true.SILENT: or whatever) which is meaningless to make.
You can use the option make --silent which will suppress output for all targets. If you want to suppress output for some commands, you can prefix them by #
I like something like this:
$(obj)environment.o: $(src)environment.c
#echo building $#
#$(CC) $(AFLAGS) -Wa, --no-warn \
-DENV_CRC=$(shell $(obj)../tools/envcrc) \
-c -o $# $(src)environment.c
The #echo ... gives a minimal status message, the '#' in front of the $(CC) suppresses standard output (but still allows error messages).
You can use this syntax : #$(CC) $(AFLAGS) -Wa, --no-warn \...
I am trying to use the following in a makefile, but when I type make filter_test it gives me the error below, and I can not figure out why. Note the spaces where the input files should be.
CXX=g++
CXXFLAGS=-O1 -pedantic -Wall -Werror -g
DEPS=p2.o recursive.o $#.cpp
p2.o: p2.cpp ; $(CXXFLAGS) -c p2.cpp
recursive.o: recursive.cpp ; $(CXXFLAGS) -c recursive.cpp
filter_test: p2.o $#.cpp recursive.o ; $(CXX) $(CXXFLAGS) recursive.o p2.o $#.cpp -o aaa
Output:
g++ -O1 -pedantic -Wall -Werror -g -o .cpp
g++: fatal error: no input files
compilation terminated.
make: *** [.cpp] Error 4
$# only has a value inside the recipe, so when make sees $# in the prerequisite list, it treats it as an empty string. So make is trying to build the pre-requisite .cpp and using the default rule to build it. To fix this just write:
filter_test: p2.o filter_test.cpp recursive.o
Leave the recipe blank and let make use default rules.
I get this error when I do the make:
relocation R_X86_64_32 against `vtable for Torch::MemoryDataSet' can not be used
when making a shared object; recompile with -fPIC
It says that I should recompile with the -fPIC option. I did that, adding
the -fPIC option to CFLAGS and CXXFLAGS, but I still get the same error. Is there any way to solve this? I have seen that this problem is related with the use of a 64-bit machine, and it is true that I am using one.
I had this problem quite a while back and if I remember correctly, the fix was moving the placement of -fPIC just after gcc in the command line. Made absolutely no sense, and less so now, but as I remember, that fixed it.
I encountered the same problem, but it had an extra twist. The answer by #clintm solved it, but I thought I would describe my variation of the problem here for future reference...
Makefile on 32-bit machine:
CXX=g++
CXXFLAGS= -O3 -Wall
...
...
%.o: %.c
$(CXX) $(CXXFLAGS) -fpic -c $<
libmylibrary.so: $(OBJECTS)
$(CXX) -shared -Wl,-soname,$# -o $# $(OBJECTS)
This compiled correctly. But the same Makefile failed when I tried it on a 64-bit machine. I changed "-fpic" to "-fPIC" and it still failed. I changed the object rule to:
%.o: %.c
$(CXX) -fPIC $(CXXFLAGS) -c $<
and it still failed.
Finally, I placed "-fPIC" in the actual compiler variable (so that now "-fPIC" appears in the rule for each object and the rule for the shared library):
CXX=g++ -fPIC
CXXFLAGS= -g -O3 -Wall
...
%.o: %.c
$(CXX) $(CXXFLAGS) -c -o $# $<
libalglib.so: $(OBJECTS)
$(CXX) -shared -Wl,-soname,$# -o $# $(OBJECTS)
And it worked!
Let's say you have some makefile like:
CFLAGS = -g -Wall
SOURCES = $(wildcard *.c)
OBJECTS = ...
TARGET = libmyawesomelib.a
all: $(TARGET) main
just add the -fPIC flag like so:
$(TARGET): CFLAGS += -fPIC
$(TARGET): $(OBJECTS)
.
.
.
so on so forth with the rest of the makefile.
I ran into this problem cross-compiling with the android-ndk toolchain. I ended up having to use
CC="$CROSS/bin/arm-linux-androideabi-gcc -pie --sysroot=$SYSROOT"
Neither -fPIC nor -fPIE worked for me in this situation.
I was cross compiling shadowsocks-libev on a CentOS 7 machine, the same problem happened to me, it works perfectly on my laptop with
CC=mipsel-unknown-linux-uclibc-gcc CXX=mipsel-unknown-linux-uclibc-g++ AR=mipsel-unknown-linux-uclibc-ar RANLIB=mipsel-unknown-linux-uclibc-ranlib make SHARED=1 CFLAGS=-fPIC
but on travis ci, it did not work, I have to add -fPIC to CC and CXX in order to get it to work
CC="mipsel-unknown-linux-uclibc-gcc -fPIC" CXX="mipsel-unknown-linux-uclibc-g++ -fPIC" AR=mipsel-unknown-linux-uclibc-ar RANLIB=mipsel-unknown-linux-uclibc-ranlib make SHARED=1
I had this issue after I upgraded gcc. I had one .o file (sqlite) that hadn't been cleaned by the Makefile and as a result I had this issue (assuming because it was compiled with an older version of gcc). After removing that file and rebuilding this error went away.
if the project you'd like to compile has a correct configure script use like this:
$ ./configure 'CFLAGS=-g -O2 -fPIC ....' --enable-some-thing
so the flag will be all the Makefile's rule ...
few days before i've need an elder ver. of VLC to compile on an x64 machine, it has a nice configure script ;-)