I'm trying to write a state machine in VHDL that will scan a 4x4 keypad. I want keyP set to 0 at the start and after a Reset. I also want the Col to be set to "1111" at the start and after a Reset.
As I'm not fully versed in VHDL programming I'm sure it's just a stupid syntax error.
The error I get is:
Error (10818): Can't infer register for "Col[0]" at Lab_7_Keypad.vhd(39) because it does not hold its value outside the clock edge
and the same for Col[1], Col[2], Col[3], and for keyP as well.
Here's my code for the start of it all. Can someone give me an idea where I've gone wrong?
Thanks
ENTITY Lab_7_Keypad IS
PORT(
nReset : IN STD_LOGIC;
clk : IN STD_LOGIC;
row : IN STD_LOGIC_VECTOR (3 downto 0);
Col : OUT STD_LOGIC_VECTOR (3 downto 0);
data : OUT STD_LOGIC_VECTOR (3 downto 0);
keyP : OUT STD_LOGIC);
END Lab_7_Keypad;
ARCHITECTURE a OF Lab_7_Keypad IS
TYPE STATE_TYPE IS ( Col1Set, Col2Set, Col3Set, Col4Set );
SIGNAL coltest : STATE_TYPE;
BEGIN
PROCESS (clk, nReset )
BEGIN
keyP <= '0';
Col <= "1111";
IF nReset = '0' THEN -- asynch Reset to zero
coltest <= Col1Set;
Col <="1111";
keyP <= '0';
ELSIF clk'EVENT AND clk = '1' THEN -- triggers on PGT
CASE coltest IS
WHEN Col1Set =>
Col <="1110";
CASE row IS
WHEN "1110"=>--row 1
data <= "0001";
keyP <= '1';
WHEN "1101"=>--row 2
data <= "0100";
keyP <= '1';
WHEN "1011"=>--row 3
data <= "0111";
keyP <= '1';
WHEN "0111"=>--row 4
data <= "1110";
keyP <= '1';
WHEN OTHERS => coltest <= Col2Set;
END CASE;
--And continues with same Case statements three more times.
Your synthesis error is due to the fact that you are assigning to both col and keyP outside of the asynchronous reset or clock edge of your process, this does not correctly describe a register. Remove these assignments and the errors should go away.
PROCESS (clk, nReset )
BEGIN
--keyP <= '0'; <------- BAD!
--Col <= "1111"; <------- BAD!
IF nReset = '0' THEN -- asynch Reset to zero
coltest <= Col1Set;
Col <="1111";
keyP <= '0';
ELSIF clk'EVENT AND clk = '1' THEN -- triggers on PGT
CASE coltest IS
WHEN Col1Set =>
Col <="1110";
CASE row IS
WHEN "1110"=>--row 1
data <= "0001";
keyP <= '1';
WHEN "1101"=>--row 2
data <= "0100";
keyP <= '1';
WHEN "1011"=>--row 3
data <= "0111";
keyP <= '1';
WHEN "0111"=>--row 4
data <= "1110";
keyP <= '1';
WHEN OTHERS => coltest <= Col2Set;
END CASE;
--And continues with same Case statements three more times.
Related
Please forgive myself if you will find some trivial errors in my code .. I'm still a beginner with VHDL.
Well, I have to deal with a serial interface from an ADC. The interface is quite simple ... there is a wire for the serial data (a frame of 24 bits), a signal DRDY that tells me when the new sample data is available and a serial clock (SCLK) that push the bit into (rising edge). Everything is running continuously...
I need to capture correctly the 24 bit of the sample, put them on a parallel bus (shift register) and provide a "data valid" signal for the blocks that will process the samples ...
Due to the fact that my system clock is x4 the frequency of the serial interface, i was thinking that doing the job with a FSM will be easy ...
When you look into the code you will see a process to capture the rising edges of the DRDY and SCLK.
Then a FSM with few states (Init, wait_drdy, wait_sclk, inc_count, check_count).
I use a counter (cnt unsigned) to check if I've already captured the 24 bits, using also to redirect the states of the FSM in "check_count" state.
Here a picture:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity serial_ads1675 is
Port (
clk : in STD_LOGIC;
reset : in STD_LOGIC;
sclk : in std_logic;
sdata : in std_logic;
drdy : in std_logic;
pdata : out std_logic_vector(23 downto 0);
pdready : out std_logic
);
end serial_ads1675;
architecture Behavioral of serial_ads1675 is
-- Internal declarations
signal ipdata : std_logic_vector (23 downto 0);
signal ipdready : std_logic;
signal tmp1, tmp2, tmp3, tmp4 : std_logic;
signal rise_drdy, rise_sclk : std_logic;
signal cnt : unsigned (4 downto 0);
type state is (init, wait_drdy, wait_sclk, inc_count, check_count);
signal actual_state, next_state : state;
begin
-- Concurrent statements
pdata <= ipdata;
pdready <= ipdready;
rise_drdy <= '1' when ((tmp1 = '1') and (tmp2 = '0')) else '0';
rise_sclk <= '1' when ((tmp3 = '1') and (tmp4 = '0')) else '0';
-- Process
process (clk, reset)
begin
if(reset = '0') then
tmp1 <= '0';
tmp2 <= '0';
tmp3 <= '0';
tmp4 <= '0';
elsif (falling_edge(clk)) then
tmp1 <= drdy;
tmp2 <= tmp1;
tmp3 <= sclk;
tmp4 <= tmp3;
end if;
end process;
process (reset, clk)
begin
if (reset = '0') then
actual_state <= init;
elsif (rising_edge(clk)) then
actual_state <= next_state;
end if;
end process;
process (rise_sclk, rise_drdy) -- Next State affectation
begin
case actual_state is
when init =>
next_state <= wait_drdy;
ipdata <= (others => '0');
ipdready <= '0';
cnt <= (others => '0');
when wait_drdy =>
if (rise_drdy = '0') then
next_state <= actual_state;
else
next_state <= wait_sclk;
end if;
cnt <= (others => '0');
when wait_sclk =>
if (rise_sclk = '0') then
next_state <= actual_state;
else
next_state <= inc_count;
end if;
ipdready <= '0';
when inc_count =>
next_state <= check_count;
cnt <= cnt + 1;
ipdready <= '0';
ipdata(23 downto 1) <= ipdata(22 downto 0);
ipdata(0) <= sdata;
when check_count =>
case cnt is
when "11000" =>
next_state <= wait_drdy;
ipdready <= '1';
when others =>
next_state <= wait_sclk;
ipdready <= '0';
end case;
when others =>
next_state <= init;
end case;
end process;
end Behavioral;
My problem is during the check_count state ...
I'm expecting that this state should last one system clock cycle, but actually it last much more.
Here a snapshot of the behavioral simulation:
Due to the fact that this state last more than expected, i miss the following SCLK pulse and don't record the next bit ...
I don't understand why this state last so many system clock cycles instead of just one ...
Anyone has some clues and bring some light in my dark night ?
Thanks in advance.
Edit: I've tried to change the signal cnt for an integer variable internal to the process of the FSM ... Same results
The error is this:
process (rise_sclk, rise_drdy) -- Next State affectation
begin
-- code omitted, but does generally this:
next_state <= SOME_VALUE;
end process;
Because the sensitivity list includes only the signals rise_sclk and rise_drdy, the process is "executed" only if any of these signals changes. You can follow this in the wave diagram.
You don't have a synchronous design running on clk. Put clk on the sensitivity list and base the decisions on the levels of rise_sclk and rise_drdy. As an excerpt:
process (clk) -- Next State affectation
begin
if rising_edge(clk) then
case actual_state is
when init =>
next_state <= wait_drdy;
-- and so on
end case;
end if;
end process;
I am trying to realize a communication between my FPGA and the HPS on the Altera DE10nano development board. To edit the vhdl i use the Quartus Prime software.
While the communication is working in general (as in i can get some data form the fpga to the hps), i have the issue of creating a proper state-machine which can add a new value to the FIFO with a different clock (in this case 12500Hz) than the base clock of 50MHz. The other clocks (100kHz and 12500Hz) are generated in a different vhdl-module.
The general idea is to write one sample every cycle of the 12,5kHz-Clock. Each cycle i've got a counter that increases as well as some data from a upstream FFT.
I'm using a simple C-Code in the HPS to read my fifo and save the read value into a .csv-file.
Now, the problem: When im using my board to load my design, I'm not getting the proper sample number. I get random values (from "counter_sample") in the .csv-file, while the simulation (with ModelSim) of the state-machine is doing what i want it to do.
Also, the design does work good when i use the 100kHz-Clock to trigger the process, but i've been told that's bad practice, since the clocks are not generated by a pll. This also leads me to thinking it is not an issue with the used C-Code.
The random values i get are not successively, but rather 200-300 counter-values apart of each other.
I'm not a veteran in programming vhdl (as you can probably tell) but will copy my state-machine below. I'm happy to hear your input and will provide further information if needed.
The fft_sop and fft_eop signals are start- and endofpacket signal from the upstream fft.
Thanks!
process(Clk_50MHz, in_reset)
begin
if (in_reset = '1') then
f2h_state <= f2h_idle;
counter_sample <=0;
counter_wait <=0;
out_fifo_write <='0';
out_fifo_writedata <= (others => '0');
fft_sop_old <= '0';
fft_eop_old <= '0';
Clk_12500Hz_alt<='0';
elsif(rising_edge(Clk_50MHz)) then
fft_sop_old <= in_fft_sop;
fft_eop_old <= in_fft_eop;
Clk_12500Hz_old <= Clk_12500Hz;
case f2h_state is
when f2h_idle =>
if ((Clk_12500Hz = '1') and (Clk_12500Hz_old = '0')) then
counter_wait <= counter_wait + 1;
if counter_wait = 8190 then
f2h_state <= f2h_wait_start;
else
f2h_state <= f2h_idle;
end if;
else
f2h_state <= f2h_idle;
end if;
when f2h_wait_start =>
out_fifo_write <= '0';
if ((in_fft_sop = '1') and (fft_sop_old = '0')) then
out_fifo_write <= '1';
out_fifo_writedata(10 downto 0) <= conv_std_logic_vector(1, 11);
counter_sample <= 2;
out_fifo_writedata(22 downto 11) <= in_fft_real(11 downto 0);
out_fifo_writedata(34 downto 23) <= in_fft_imag(11 downto 0);
out_fifo_writedata(63 downto 35) <= (others => '0');
f2h_state <= f2h_writesample;
end if;
when f2h_writesample =>
if ((Clk_12500Hz = '1') and (Clk_12500Hz_old = '0')) then
out_fifo_write <= '1';
counter_sample <= counter_sample + 1;
out_fifo_writedata(10 downto 0) <= conv_std_logic_vector(counter_sample, 11);
out_fifo_writedata(22 downto 11) <= in_fft_real(11 downto 0);
out_fifo_writedata(34 downto 23) <= in_fft_imag(11 downto 0);
out_fifo_writedata(63 downto 35) <= (others => '0');
if in_fft_eop = '1' then
f2h_state <= f2h_wait_start;
end if;
f2h_state <= f2h_writesample;
else
out_fifo_write <= '0';
end if;
end case;
end if;
end process;
All three states are rightly synchronised to the system clock clk_50MHz, but the first and third states, F2H_IDLE and F2H_WRITESAMPLE, are looking for the rising edge of clk_12500Hz while your second state F2H_WAIT_START isn't. Instead, it's only looking for the rising edge of in_fft_sop. This means that the first and third states are synchronised to the rising edge of the clk_12500Hz signal, but the second state is not synchronised to the clk_12500Hz signal (only the in_fft_sop signal). Is this what you intended? This could explain why you are getting random values on counter_sample.
I've restructured the logic so that all the states are synchronised to both the system clock clk_50MHz and the clk_12500Hz signal, which is what I understood from your question, and I've assumed that new data is simply clocked into the FIFO when out_fifo_write is high.
I've also added three edge detectors to make the code more readable, and changed the level detector in the third state to a rising edge detector.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity FPGA2HPS is
port
(
clk_50MHz: in std_logic;
clk_12500Hz: in std_logic;
in_reset: in std_logic;
in_fft_sop: in std_logic;
in_fft_eop: in std_logic;
in_fft_real: in std_logic_vector(11 downto 0);
in_fft_imag: in std_logic_vector(11 downto 0);
out_fifo_write: out std_logic;
out_fifo_writedata: out std_logic_vector(63 downto 0)
);
end entity;
architecture V1 of FPGA2HPS is
type F2H_STATES is (F2H_IDLE, F2H_WAIT_START, F2H_WRITESAMPLE);
signal f2h_state: F2H_STATES;
signal rising_edge_clk_12500Hz: std_logic;
signal rising_edge_in_fft_sop: std_logic;
signal rising_edge_in_fft_eop: std_logic;
signal clk_12500Hz_old: std_logic;
signal fft_sop_old: std_logic;
signal fft_eop_old: std_logic;
signal clk_12500Hz_alt: std_logic;
signal counter_sample: integer;
signal counter_wait: integer;
begin
--
-- Rising edge detectors
--
rising_edge_clk_12500Hz <= clk_12500Hz and not clk_12500Hz_old;
rising_edge_in_fft_sop <= in_fft_sop and not fft_sop_old;
rising_edge_in_fft_eop <= in_fft_eop and not fft_eop_old;
process(clk_50MHz, in_reset)
begin
if in_reset then
f2h_state <= F2H_IDLE;
counter_sample <= 0;
counter_wait <= 0;
out_fifo_write <= '0';
out_fifo_writedata <= (others => '0');
fft_sop_old <= '0';
fft_eop_old <= '0';
clk_12500Hz_alt <= '0';
elsif rising_edge(clk_50MHz) then
-- Ensure all the state machine logic works on the rising edge of the clk_12500Hz signal while also synchronised to the clk_50MHz clock.
if rising_edge_clk_12500Hz then
fft_sop_old <= in_fft_sop;
fft_eop_old <= in_fft_eop;
clk_12500Hz_old <= clk_12500Hz;
case f2h_state is
when F2H_IDLE =>
f2h_state <= F2H_IDLE;
counter_wait <= counter_wait + 1;
if counter_wait = 8190 then
f2h_state <= F2H_WAIT_START;
end if;
when F2H_WAIT_START =>
f2h_state <= F2H_WAIT_START;
out_fifo_write <= '0';
if rising_edge_in_fft_sop then
out_fifo_write <= '1';
out_fifo_writedata(10 downto 0) <= std_logic_vector(to_unsigned(1, 11)); -- CHANGED
counter_sample <= 2;
out_fifo_writedata(22 downto 11) <= in_fft_real(11 downto 0);
out_fifo_writedata(34 downto 23) <= in_fft_imag(11 downto 0);
out_fifo_writedata(63 downto 35) <= (others => '0');
f2h_state <= F2H_WRITESAMPLE;
end if;
when F2H_WRITESAMPLE =>
f2h_state <= F2H_WRITESAMPLE;
counter_sample <= counter_sample + 1;
out_fifo_writedata(10 downto 0) <= std_logic_vector(to_unsigned(counter_sample, 11)); -- CHANGED
out_fifo_writedata(22 downto 11) <= in_fft_real(11 downto 0);
out_fifo_writedata(34 downto 23) <= in_fft_imag(11 downto 0);
out_fifo_writedata(63 downto 35) <= (others => '0');
if rising_edge_in_fft_eop then -- CHANGED: Should this be on the rising edge of in_fft_eop?
out_fifo_write <= '0'; -- ADDED: End of write mode?
f2h_state <= F2H_WAIT_START;
end if;
end case;
end if;
end if;
end process;
end architecture;
I hope that helps, but without the timing diagrams of the FFT and FIFO nor a test bench, I haven't been able to simulate it.
I have to do UART with vhdl on the Xilinx which will send 16 chars string. I wrote such code
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.numeric_std.ALL;
entity uartByJackob is
Port ( CLK, A, B, C : in STD_LOGIC;
RESET : in STD_LOGIC;
TxD, TxDOSC : out STD_LOGIC);
end uartByJackob;
architecture Behavioral of uartByJackob is
signal K: std_logic_vector(14 downto 0);
signal Q: std_logic_vector(3 downto 0);
signal CLK_Txd: std_logic;
signal ENABLE: std_logic;
signal QTxD: std_logic_vector(9 downto 0);
signal DATA : STD_LOGIC_VECTOR(7 downto 0);
-- freq of clock
begin
process(CLK, RESET)
begin
if rising_edge(CLK) then
if(A = '1' and K < 10416) then
K <= K + 1;
CLK_Txd <= K(13);
elsif(B = '1' and K < 5208) then
K <= K + 1;
CLK_Txd <= K(12);
elsif(C = '1' and K < 20832) then
K <= K + 1;
CLK_Txd <= K(14);
else
K <= (others => '0');
end if;
end if;
end process;
--counter
process(CLK_Txd, RESET, ENABLE)
begin
if(RESET = '1' and ENABLE = '0') then
Q <= "0000";
elsif (rising_edge(CLK_Txd)) then
Q <= Q + 1;
end if;
end process;
--comparator
ENABLE <= '1' when (Q > 4) else '0';
--transcoder
process(Q, CLK_Txd)
begin
if (rising_edge(CLK_Txd)) then
case Q is
when "0001" => DATA <= x"40";
when "0010" => DATA <= x"41";
when "0011" => DATA <= x"42";
when "0100" => DATA <= x"43";
when "0101" => DATA <= x"44";
when "0110" => DATA <= x"45";
when "0111" => DATA <= x"46";
when "1000" => DATA <= x"47";
when "1001" => DATA <= x"48";
when "1010" => DATA <= x"49";
when "1011" => DATA <= x"50";
when "1100" => DATA <= x"51";
when "1101" => DATA <= x"52";
when "1110" => DATA <= x"53";
when "1111" => DATA <= x"54";
when others => DATA <= x"55";
end case;
end if;
end process;
--uart
process(CLK_Txd, ENABLE, DATA)
begin
if(ENABLE = '0') then
QTxD <= DATA & "01";
elsif rising_edge(CLK_Txd) then
QTxD <= '1'&QTxD(9 downto 1);
end if;
end process;
TxD <= QTxD(0);
TxDOSC <= QTxD(0);
end Behavioral;
It's send data completely not connected with that what i have in transcoder and realy dont know why. Do you have any ideas what is wrong with my code, or do you have any diffrent examples of it how to send your own 16 chars with uart? I suppose that something is wrong with my counter or comparator.
--EDIT
Thans for your effort, i can't try your code at the Xilinx right now couse I am workin on it at my university. I see that you made a lot of changes in my code. Of course first i try to do it like you show and i hope this will be acceptable, but I propably have to do it with transcoder according to this picture.
From last time i made such changes i my code
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.numeric_std.ALL;
entity uartByJackob is
Port ( CLK, A, B, C : in STD_LOGIC;
RESET : in STD_LOGIC;
TxD, TxDOSC : out STD_LOGIC);
end uartByJackob;
architecture Behavioral of uartByJackob is
signal K: std_logic_vector(14 downto 0);
signal Q: std_logic_vector(7 downto 0);
signal CLK_Txd: std_logic;
signal ENABLE: std_logic;
signal QTxD: std_logic_vector(7 downto 0);
signal DATA : STD_LOGIC_VECTOR(7 downto 0);
signal QPrim: std_logic_vector(3 downto 0);
begin
process(CLK, RESET)
begin
CLK_Txd <= CLK;
end process;
process(CLK_Txd, RESET, ENABLE)
begin
if(ENABLE = '0') then
Q <= "00000000";
elsif (rising_edge(CLK_Txd)) then
Q <= Q + 1;
end if;
end process;
ENABLE <= '1' when (Q <= 255) else '0';
process(Q(7 downto 4))
begin
case Q(7 downto 4) is
when "0000" => DATA <= x"40";
when "0001" => DATA <= x"41";
when "0010" => DATA <= x"42";
when "0011" => DATA <= x"43";
when "0100" => DATA <= x"44";
when "0101" => DATA <= x"45";
when "0110" => DATA <= x"46";
when "0111" => DATA <= x"47";
when "1000" => DATA <= x"48";
when "1001" => DATA <= x"49";
when "1010" => DATA <= x"50";
when "1011" => DATA <= x"51";
when "1100" => DATA <= x"52";
when "1101" => DATA <= x"53";
when "1110" => DATA <= x"54";
when "1111" => DATA <= x"55";
when others => DATA <= x"56";
end case;
end process;
process(CLK_Txd, ENABLE, DATA)
begin
if(ENABLE = '1') then
QTxD <= DATA;
elsif rising_edge(CLK_Txd) then
QTxD <= '1'&QTxD(7 downto 1);
end if;
end process;
TxD <= QTxD(0);
TxDOSC <= QTxD(0);
end Behavioral;
According to that i send MSB to transcoder and LSB to comparator but my program all the time still send x"40" to DATA and it is propably connected with this counter which you were talking about.
There is my simulation efect. I becoming upset with that couse i don't have enough skills in vhdl to do it by my self. I hope that you will help me to do rebuild my project. On simulation it looks good i dont know how it looks on Xilinx.
Can you show me a piece of code? - Stefan
The entire purpose to providing the link to Adrian Adamcyzk's code (Altera FPGA hardware (has an issue) vs ModelSim simulation (ok) - self implemented UART) was to provide an example with a bit (baud) counter and flip flop used to control sending the message once.
Here's Jackob's modified:
library ieee;
use ieee.std_logic_1164.all;
-- use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity uartbyjackob is
port (
clk, a, b, c: in std_logic;
reset: in std_logic;
txd, txdosc: out std_logic
);
end entity uartbyjackob;
architecture foo of uartbyjackob is
-- signal k: unsigned(14 downto 0); -- FOR simulation
-- note if k were used in simulation it would require initialization
signal q: unsigned (3 downto 0); -- WAS std_logic_vector
signal clk_txd: std_logic;
signal enable: std_logic;
signal qtxd: std_logic_vector(9 downto 0);
-- signal data: std_logic_vector(7 downto 0);
-- added:
signal bdcnt: unsigned (3 downto 0);
signal ldqtxd: std_logic;
signal davl: std_logic;
type data_lut is array (0 to 15) of std_logic_vector (7 downto 0);
constant data: data_lut := (
x"40", x"41", x"42", x"43", x"44", x"45", x"46", x"47",
x"48", x"49", x"50", X"51", x"52", X"53", x"54", x"55"
);
signal datalut: std_logic_vector (7 downto 0); -- FOR SIMULATION visibility
begin
-- -- freq of clock -- NOTE k never in known binary state for simulation
-- process (clk, reset)
-- begin
-- if rising_edge(clk) then
-- if a = '1' and k < 10416 then
-- k <= k + 1;
-- clk_txd <= k(13);
-- elsif b = '1' and k < 5208 then
-- k <= k + 1;
-- clk_txd <= k(12);
-- elsif c = '1' and k < 20832 then
-- k <= k + 1;
-- clk_txd <= k(14);
-- else
-- k <= (others => '0');
-- end if;
-- end if;
-- end process;
clk_txd <= clk; -- SHORTENS SIMULATION
DAVL_FF: -- DATA_AVAILABLE to send
process (clk_txd, reset)
begin
if reset = '1' then
davl <= '0';
elsif rising_edge (clk_txd) then
if q = 15 and bdcnt = 9 then -- a JK FF equivalent
davl <= '0';
elsif q = 0 then
davl <= '1'; -- one clock holderover from reset
-- else
-- davl <= davl;
end if;
end if;
end process;
-- process(clk_txd, reset, enable)
-- begin
-- if reset = '1' and enable = '0' then
-- q <= "0000";
-- elsif rising_edge(clk_txd) then
-- q <= q + 1;
-- end if;
-- end process;
QCNT:
process (clk_txd, reset)
begin
if reset = '1' then
q <= (others => '0');
elsif rising_edge (clk_txd) then
if enable = '1' then
q <= q + 1;
end if;
end if;
end process;
BAUD_COUNTER:
process (clk_txd, reset)
begin
if reset = '1' then
bdcnt <= (others => '0');
elsif rising_edge (clk_txd) then
if davl = '0' or bdcnt = 9 then
bdcnt <= (others => '0');
else
bdcnt <= bdcnt + 1;
end if;
end if;
end process;
-- comparator
-- enable <= '1' when (q > 4) else '0';
enable <= '1' when bdcnt = 9 and davl = '1' and q /= 15 else
'0';
-- q latches at 15;
ldqtxd <= '1' when bdcnt = 9 and davl = '1' else
'0';
datalut <= data(to_integer(q)); -- FOR SIMULATION VISIBILITIY
--transcoder
-- process(q, clk_txd)
-- begin
-- if rising_edge(clk_txd) then
-- case q is
-- when "0001" => data <= x"40";
-- when "0010" => data <= x"41";
-- when "0011" => data <= x"42";
-- when "0100" => data <= x"43";
-- when "0101" => data <= x"44";
-- when "0110" => data <= x"45";
-- when "0111" => data <= x"46";
-- when "1000" => data <= x"47";
-- when "1001" => data <= x"48";
-- when "1010" => data <= x"49";
-- when "1011" => data <= x"50";
-- when "1100" => data <= x"51";
-- when "1101" => data <= x"52";
-- when "1110" => data <= x"53";
-- when "1111" => data <= x"54";
-- when others => data <= x"55";
-- end case;
-- end if;
-- end process;
-- uart
-- process (clk_txd, enable, data)
-- begin
-- if enable = '0' then
-- qtxd <= data & "01";
-- elsif rising_edge(clk_txd) then
-- qtxd <= '1' & qtxd(9 downto 1);
-- end if;
-- end process;
TX_SHIFT_REG:
process (clk_txd, reset) -- shift regiseter Tx UART
begin
if reset = '1' then
qtxd <= (others => '1'); -- output mark by default
elsif rising_edge (clk_txd) then
if ldqtxd = '1' then
qtxd <= '1' & data(to_integer(q)) & '0';
-- STOP & Data(q) 7 downto 0 & START , a MUX and expansion
else
qtxd <= '1' & qtxd(9 downto 1); -- shift out;
end if;
end if;
end process;
txd <= qtxd(0);
txdosc <= qtxd(0);
end architecture foo;
library ieee;
use ieee.std_logic_1164.all;
entity uartbyjackob_tb is
end entity;
architecture foo of uartbyjackob_tb is
signal clk: std_logic := '0';
signal reset: std_logic := '0';
signal txd: std_logic;
begin
DUT:
entity work.uartbyjackob
port map (
clk => clk, -- clk_txd driven by clk
a => 'X',
b => 'X',
c => 'X', -- a, b, c aren't used
reset => reset,
txd => txd,
txdosc => open
);
CLOCK:
process
begin
wait for 52.35 us;
clk <= not clk;
if now > 20000 us then
wait;
end if;
end process;
STIMULUS:
process
begin
wait for 104.7 us;
reset <= '1';
wait for 104.7 us;
reset <= '0';
wait;
end process;
end architecture;
The model has been modified for faster simulation, ignoring the baud rate clock generator.
There's an added flip flop (davl) for enabling the UART to run. There's an added baud (bit) counter bdcnt.
I changed the order of the start, stop and data values loaded into QTxD so the start bit came out first, followed by 8 data bits and the stop bit.
You can read off TxD from left to right start bit, data(q)(0) ... data(q(7), stop bit. The enable or ldqtxd will occur at the same time as a stop bit.
There's only one observable draw back to this implementation, if you reset while a value in the shift register hasn't finished loading you'll cause a framing error for the receiver. Don't reset it for 10 baud times after davl goes false.
The simulation is shown with a 9600 baud clk_txd, the characters go out back to back.
It has fewer flip flops than the original (disregarding k). There is no data register separate from QTxD ( - 8 FFs) plus bdcnt (+ 4) plus davl (+ 1). There are two comparisons (optimized to two) bdcnt = 9, q =, /= 9. Those could be expressed separately so it doesn't require optimization during synthesis.
I changed the look up table style, a matter of personal preference also the excuse for changing counters to type unsigned and using only package numeric_std for arithmetic.
The little testbench likewise doesn't expect the k counter to generate the baud clock.
Running the testbench gives:
Where there's an added signal datalut to show the value being shifted out after ldqtxd.
After your change making the q counter (7 downto 0)
We still see from your waveform that it doesn't work.
This is due to the enable and the shift register.
If you use a single counter with the upper four bits indexing the output character your character is transmitted in 10 out of the 16 clk_txd times indexed by the lower four bits of the counter. The remaining clock times TxD should be '1' (idle line marks in RS-232 parlance).
The order for data to be transmitted will be a space (the start bit), data(0) through data(7) and a mark (the stop bit). (Shown left to right on TxD).
For simulation the k counter is not used. I included it commented out below.
I made several changes for proper simulation. These include synchronously loading the shift register containing QTxD, synchronously clearing the rightmost bit of QTxD to provide a full width and moving enable to occur once every sixteen clocks (clk_txd). The enable is preceded by a new clear for the start bit and both been offset to prevent it from occurring during reset which has the effect of causing a framing error on the first character for any receiver.
Simulation is done with the same testbench I provide above.
The changes to your new code are shown by comments:
architecture behavioral of uartbyjackob is
-- signal k: std_logic_vector(14 downto 0);
signal q: unsigned (7 downto 0); -- std_logic_vector(7 downto 0);
signal clk_txd: std_logic;
signal enable: std_logic;
signal qtxd: std_logic_vector(7 downto 0);
-- using an 8 bit shift register requires a method of outputting a
-- synchronous start bit (the width is important for receive framing)
-- and synchronous stop bit
signal data: std_logic_vector(7 downto 0);
signal qprim: std_logic_vector(3 downto 0);
signal clear: std_logic; -- synchronous clear for start bit
begin
-- let's keep this here for when you put it the FPGA
-- -- freq of clock -- NOTE k never in known binary state for simulation
-- process (clk, reset)
-- begin
-- if rising_edge(clk then
-- if a = '1' and k < 10416 then
-- k <= k + 1;
-- clk_txd <= k(13);
-- elsif b = '1' and k < 5208 then
-- k <= k + 1;
-- clk_txd <= k(12);
-- elsif c = '1' and k < 20832 then
-- k <= k + 1;
-- clk_txd <= k(14);
-- else
-- k <= (others => '0');
-- end if;
-- end if;
-- end process;
process (clk) -- , reset)
begin
clk_txd <= clk; -- if simply a concurrent assignment statement this
end process; -- would look similar to the elaborated equivalent
-- process. The difference, no sensitivity list and
-- an explict wait on clk statement at the end.
-- This process wants to be removed and replaced by
-- the above commented out process for synthesis
process (clk_txd, reset) -- , reset, enable) -- enable a reset?
begin
-- if enable = '0' then
if reset = '1' then -- puts q counter in known state for simulation
q <= "00000000";
elsif rising_edge(clk_txd) then
if q /= 255 then -- stop after sending once
q <= q + 1;
end if;
end if;
end process;
-- enable <= '1' when q <= 255 else '0'; -- this appears incorrect
enable <= '1' when q(3 downto 0) = "0010" else
'0';
clear <= '1' when q(3 downto 0) = "0001" else
'0';
-- USING ONE COUNTER requires some clocks output MARKS
-- (idle bits) each 16 clocks. It requires the load (enable)
-- occur once every 16 clocks.
-- q(3 downto 0) is selected for enable to prevent outputting spaces
-- TxD during reset (q is reset to all '0's). This would cause a receive
-- framing error.
process (q(7 downto 4))
begin
case q(7 downto 4) is
when "0000" => data <= x"40";
when "0001" => data <= x"41";
when "0010" => data <= x"42";
when "0011" => data <= x"43";
when "0100" => data <= x"44";
when "0101" => data <= x"45";
when "0110" => data <= x"46";
when "0111" => data <= x"47";
when "1000" => data <= x"48";
when "1001" => data <= x"49";
when "1010" => data <= x"50";
when "1011" => data <= x"51";
when "1100" => data <= x"52";
when "1101" => data <= x"53";
when "1110" => data <= x"54";
when "1111" => data <= x"55";
when others => data <= x"56";
end case;
end process;
process (clk_txd) -- , enable, data) -- synchronous enable and clear
begin
-- if enable = '1' then -- this appears incorrect
-- qtxd <= data;
if reset = '1' then
qtxd <= (others => '1'); -- outputs mark after reset
elsif rising_edge(clk_txd) then
if clear = '1' then -- synchronous clear for start bit
qtxd(0) <= '0';
elsif enable = '1' then -- synchronous load
qtxd <= data;
else
qtxd <= '1' & qtxd(7 downto 1); -- shift right
end if;
end if;
end process;
-- the synchronous load prevents the first start bit from being stretched
-- q(3 downto 0) the following in hex notation
-- q(3 downto 0) = 2 is the start bit
-- = 3 is data(0)
-- ...
-- = A is data(7)
-- = B is the stop bit
-- = C - 1 are mark (idle) bits (q(3 downto 0) rolls over)
-- = 1 enable occurs loading qtxd
--
-- The offset is caused by synchronous load (1 clk_txd) and the load point
-- (q(3 downto 0) = 1 in enable term).
--
-- The load point wants to occur in the first 6 counts of q(3 downto 0) to
-- insure a trailing mark when q is stopped.
--
-- q(3 downto 0) = 1 is selected for enable to prevent spurious spaces
-- during reset from causing a receive framing error.
txd <= qtxd(0);
txdosc <= qtxd(0);
end architecture behavioral;
The comment table:
-- the synchronous load prevents the first start bit from being stretched
-- q(3 downto 0) the following in hex notation
-- q(3 downto 0) = 2 is the start bit
-- = 3 is data(0)
-- ...
-- = A is data(7)
-- = B is the stop bit
-- = C - 1 are mark (idle) bits (q(3 downto 0) rolls over)
-- = 1 enable occurs loading qtxd
--
-- The offset is caused by synchronous load (1 clk_txd) and the load point
-- (q(3 downto 0) = 1 in enable term).
--
-- The load point wants to occur in the first 6 counts of q(3 downto 0) to
-- insure a trailing mark when q is stopped.
--
-- q(3 downto 0) = 1 is selected for enable to prevent spurious spaces
-- during reset from causing a receive framing error.
tells you where to find bits of the data(q(7 downto 0)) selected character. In the following waveform q is shown as hex to match:
You'll find with the fixes the first character transmitted is 0x40, the second 0x41,...
i'm trying to make my own I2C communication and i have a problem with multiply drivers, it's not like i don't understand them i just don't see them (i'm still fresh at vhdl), so please just take a look at my code and tell mi why is there such mistake.
i try to operate on flags to have multiple signal drivers on bus but there's just something not right. The multiple drivers are on scl, sda, start_clk and stop_clk. Is it because those flags are for example in two different processes?
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity I2C_com is
port (
reset_en: in std_logic;
clk: in std_logic;
sda: inout std_logic;
scl: out std_logic;
RD:in std_logic;
WR: in std_logic;
addr: buffer std_logic_vector(7 downto 0)
);
end I2C_com;
architecture MAIN of I2C_com is
signal data :std_logic_vector (12 downto 0):="0000000000010";
signal i2c_clk: std_logic ;
signal clk_count : unsigned(19 downto 0):="00000000000000000100";
type program_state is (start,init,error_rd_wr,slave,ack);
signal state: program_state;
signal write_data: std_logic_vector (7 downto 0):=(others => '0');
signal read_data: std_logic_vector (7 downto 0):=(others => '0');
signal clk_enable: std_logic;
signal reset: std_logic:='1';
signal start_clk: std_logic:= 'Z';
signal stop_clk: std_logic:= 'Z';
signal strech: std_logic := '0';
signal cnt_addr: integer := 0;
signal ack_error: std_logic;
signal sda_data: std_logic;
signal start_data: std_logic:= 'Z';
begin
i2c_clock: process(clk,reset_en,reset)
begin
if reset_en = '1' or reset = '1' then
elsif falling_edge(clk) then
if clk_count < unsigned(data) then
clk_count <= clk_count + 1;
clk_enable <= '1';
else
clk_count <= x"00000";
clk_enable <= '0';
end if;
i2c_clk <= clk_enable;
if start_clk = '1' then
sda <= '0';
scl <= '0';
start_clk <= '0';
end if;
if stop_clk = '1' then
sda <= '0';
scl <= '0';
stop_clk <= '0';
end if;
end if;
end process i2c_clock;
--
process(i2c_clk,reset_en,reset)
begin
if reset_en = '1' or reset = '1' then
reset <= '0';
cnt_addr <= 0;
state <= init;
elsif rising_edge(i2c_clk) then
case state is
when init =>
if RD = '1' or WR = '1' then
state <= start;
else
state <= error_rd_wr;
end if;
when start =>
start_clk <= '1';
state <= slave;
when slave =>
start_data <= '1';
if cnt_addr < 8 then
sda_data <= addr(cnt_addr);
cnt_addr <= cnt_addr + 1;
else
cnt_addr <= 0;
state <= ack;
end if;
when error_rd_wr =>
reset <= '1';
when ack =>
start_data <= '0';
ack_error <= sda;
if ack_error = '1' then
stop_clk <= '1';
reset <= '1';
else
end if;
if RD = '1' then
elsif WR = '1' then
else
stop_clk <= '1';
reset <= '1';
end if;
end case;
end if;
end process;
sda <= sda_data when start_data = '1' else 'Z';
scl <= i2c_clk when start_clk = '0' and stop_clk = '0' else 'Z';
end MAIN;
A signal for synthesis can be driven from only one process or one continuous assign; for simulation multiple drivers are possible using resolved signals like std_logic.
The scl and sda are driven both from the i2c_clock process and the continuous assign in the end of the file.
The start_clk and stop_clk are driven both from the i2c_clock process and the other unnamed process.
One possibility for scl and sda is to only drive these from the continuous assign, since synthesis tools often prefer tri-state output to be written like:
q <= value when en = '1' else 'Z';
I have some troubles with my nexys 3 vhdl driver for the Pmod TMP. I would like to communicate with via SPI 3 wire (Clock, Reset and DQ (MISO/MOSI)) so I've wrote some code lines and test it using the leds to display receive data. But That don't work and I don't know why... I've made a state machine that, if it's the first time, send the configuration data and then send the word "start" to start convert, then I pass in receive configuration and take the convert data (temperature in binary) and finally send the "stop" word. And that start again without the send configuration because it's not the first time.
My state machine don't work, there is not receive data and I don't know why.
I'll be glad if you could help me.
Best regards.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity SPI is
port(
CLK : in std_logic;
RST : in std_logic;
SPI_SCK : out std_logic;
SPI_DQ: inout std_logic;
SPI_RST : out std_logic;
LED : out std_logic_vector(7 downto 0) :="00000000"
);
end entity SPI;
architecture behavioral of SPI is
type State is ( IDLE , sendConf, sendBit , receiveBit, clockHigh , resetHigh);
signal States : State := IDLE;
signal Counter : integer range 0 to 15 := 0;
signal data_reg : std_logic_vector(15 downto 0):="0000000000000000";
signal data : std_logic_vector(8 downto 0):="000000000";
signal data_trans : std_logic_vector(7 downto 0):="00000000";
signal first_time : std_logic := '1';
signal send : std_logic := '0';
signal receive : std_logic := '0';
signal right : std_logic := '0';
begin
process(CLK, RST)
variable conf : std_logic_vector(15 downto 0):= "0000110000000011";
variable start: std_logic_vector(7 downto 0):= "01010001";
variable stop : std_logic_vector(7 downto 0):= "00100010";
begin
if rising_edge(CLK) then
if RST = '1' then
States <= IDLE;
first_time <= '1';
else
case States is
when IDLE =>
SPI_RST <= '1';
SPI_SCK <= '0';
Counter <= 0;
if first_time = '1' then
data_reg <= conf;
send <= '1';
first_time <= '0';
States <= sendConf;
else
if send = '1' then
data_trans <= start;
send <= '0';
receive <= '1';
right <= '0';
States <= sendBit;
elsif receive = '1' then
receive <= '0';
right <= '1';
States <= receiveBit;
elsif send = '0' and receive = '0' then
data_trans <= stop;
send <= '1';
right <= '0';
States <= sendBit;
end if;
end if;
when sendConf =>
SPI_SCK <= '0';
SPI_DQ <= data_reg(15);
data_reg <= data_reg(14 downto 0) & "0";
States <= clockHigh;
when sendBit =>
SPI_SCK <= '0';
SPI_DQ <= data_trans(7);
data_trans <= data_trans(6 downto 0) & "0";
States <= clockHigh;
when receiveBit =>
SPI_SCK <= '0';
data <= data(7 downto 0) & SPI_DQ;
States <= clockHigh;
when clockHigh =>
SPI_SCK <= '1';
if first_time = '1' then
if Counter = 16 then
States <= resetHigh;
else
Counter <= Counter + 1;
States <= sendConf;
end if;
else
if right = '1' then
if Counter = 9 then
States <= resetHigh;
else
Counter <= Counter + 1;
States <= sendBit;
end if;
else
if Counter = 8 then
States <= resetHigh;
else
Counter <= Counter + 1;
States <= sendBit;
end if;
end if;
end if;
when resetHigh =>
SPI_RST <= '0';
States <= IDLE;
end case;
end if;
end if;
end process;
end architecture behavioral;`
The Maxim DS1626 does not communicate via SPI interface. So please look into data sheet pages 4, 5 and 10, 11. These timing diagrams are very different from SPI or I²C or whatever.