How do includee all libraries from a directory in a Makefile?
Say I want to include all libraries in the directory /libdir, how would I do this?
The result should be something like:
INCLUDES = -I/libdir/lib1 -I/libdir/lib2 -I/libdir/lib3 ...
LIBDIRS = $(wildcard /libdir/*)
INCLUDES = $(addprefix -I, $(LIBDIRS))
Related
My makefile has the following section:
SRCS = src/main.c src/sdlshape.c src/sdlevent.c
OBJS = bin/main.o bin/sdlshape.o bin/sdlevent.o
Is there a way I could use a separate variable to substitute the src/ and bin/ folders in these variables?
I am not sure what exactly you are looking for, but maybe you can do something like this
SRC = src
SRCS = $(SRC)/main.c $(SRC)/sdlshape.c $(SRC)/sdlevent.c
another approach is to use $(wildcard ... ).
If you are looking for a sample of Makefile where you have different folders for includes, objects, etc., take a look here: http://www.owsiak.org/fortran-and-gnu-make/
I know it's Fortran based, but you can still get the feeling of how to structure it.
I am currently have an Android.mk file. For some requirement I need to write a standard GNU make file to build the same program.
As you know in Android native build, we simply put all source files together like
LOCAL_SRC_FILES := a.c b.c d.cpp e.cpp
Now I want to do something in Makefile like:
OBJ = $(LOCAL_SRC_FILES: .c=.o)
This will only transform .c files with .o object targets. How can I combine the condition ".c or .cpp" together?
I think I am too busy to forget that I can just achieve this target by execute this function twice.
TMP_OBJ = $(LOCAL_SRC_FILES: .c=.o)
OBJ = $(TMP_OBJ: .cpp=.o)
Sorry for this silly question.
You could use basename:
OBJ := $(addsuffix .o,$(basename $(LOCAL_SRC_FILES)))
(strips off the suffix of each file in LOCAL_SRC_FILES then adds .o to the end)
Doing it in two steps:
SRC := main.c hello.cpp
OBJ := $(SRC:.c=.o)
OBJ := $(OBJ:.cpp=.o)
I'm new to makefiles , recently I was looking at a makefile and could not understand what this means
OBJS := $(SRCS:$(SRCDIR)/%.cpp=$(OBJDIR)/%.o)
where
PROJECT_ROOT=.
EXTERNAL_ROOT=$(PROJECT_ROOT)/external
SRCDIR = $(PROJECT_ROOT)/src
OBJDIR = $(PROJECT_ROOT)/myobjs
BINDIR = $(PROJECT_ROOT)/mybins
DOCDIR = $(PROJECT_ROOT)/doc
what does it represent? Also i wish to make static library consistly of all files in in the myobjs folder or $(OBJS) except main.o a file in it how to write the command
ar -cvq mylibs/libCS296test.a $(OBJS); for such a case?
Please create different SO requests for very different questions.
For your first question, that is equivalent to this function:
$(patsubst $(SRCDIR)/%.cpp,$(OBJDIR)/%.o,$(SOURCES))
which basically says "look through the value of the $(SOURCES) variable and for every word matching the pattern $(SRCDIR)/%.cpp, replace it with the pattern $(OBJDIR)/%.o. So, if SOURCES contained a word ./external/src/foo/bar/biz.cpp that would be replaced with ./external/myobjs/foo/bar/biz.o.
I usually use this line OBJECTS = $(SOURCES:.cpp=.o) to substitute the .cpp extension of files in SOURCES to .o extension.
My project now has files with .c extension together with .cpp. How do I modify that line to make it substitute all .c and .cpp extensions to .o?
I would not prefer a two lines solution like below:
OBJECTS_TMP = $(SOURCES:.cpp=.o)
OBJECTS = $(OBJECT_TMP:.c=.o)
I would like something like
OBJECTS = $(SOURCES:(.cpp|.c)=.o)
or even
OBJECTS = $(SOURCES:.*=.o)
Is that possible and how? Thanks!
You can't do it only with the shorthand. You'll have to use the patsubst function:
OBJECTS = $(patsubst %.cpp,%.o,$(patsubst %.c,%.o,$(SOURCES)))
Or you can use one of each:
OBJECTS = $(patsubst %.cpp,%.o,$(SOURCES:.c=.o))
Or, you can do it like this:
OBJECTS = $(addsuffix .o,$(basename $(SOURCES)))
I'm trying to develop a program that uses another internal library done in the same project.
I want to link both. The lib is stored and succesfully compiled under ./lib/mylib and a mylib.a is created. The issue is that I need to include ./lib/mylib directory in the INCLUDE search and also link the program against the library.
Are there any automatically defined variables or do I have to do it by my own like in the Makefile.am below?
SUBDIRS = lib .
# set the include path found by configure
INCLUDES = $(all_includes) -Ilib/mylib
bin_PROGRAMS = myprogram
myprogram_SOURCES = main.c
myprogram_CPPFLAGS = $(libmylib_CFLAGS) $(AM_CFLAGS) $(CFLAGS)
nfc_network_config_LDADD =$(LIB_MYLIB)
Your Makefile could look something like this.
SUBDIRS = lib .
bin_PROGRAMS = myprogram
myprogram_SOURCES = main.c
myprogram_CPPFLAGS = -Ilib/mylib $(AM_CPPFLAGS)
myprogram_LDADD = lib/mylib/mylib.a
Note that *_CPPFLAGS should usually not be mixed with *_CFLAGS, and that the $(CFLAGS) and $(CPPFLAGS) variables are always used (they are user variables) so you should not have to mention them. Also INCLUDES is an obsolete variable (you should use *_CPPFLAGS instead), and automake will warn about it if you run it with the -Wall option.