How to make my makefile more general? - makefile

I have a makefile which, when I need to add another file that is a part of the project, I also need to edit heavily to make it all work. I would like to just code my makefile once and be done with it! So, this is the script:
CC=g++
CFLAGS=-c -Wall
#All paths start in the main directory which has this makefile, object/ and code/.
OBJPATH=object#All compiled .o files need to be placed here.
CODEPATH=code#All .cpp and .hpp header files reside here.
#The names of all the object files that need to be made.
OBJ=$(OBJPATH)/World.o $(OBJPATH)/Block.o $(OBJPATH)/Creep.o $(OBJPATH)/Food.o $(OBJPATH)/Brick.o
all : World.a
$(OBJPATH)/World.o : $(CODEPATH)/World.hpp $(CODEPATH)/World.cpp
$(CC) $(CFLAGS) $(CODEPATH)/World.cpp
mv World.o $(OBJPATH)/
$(OBJPATH)/Block.o : $(CODEPATH)/Block.hpp $(CODEPATH)/Block.cpp
$(CC) $(CFLAGS) $(CODEPATH)/Block.cpp
mv Block.o $(OBJPATH)/
$(OBJPATH)/Creep.o : $(CODEPATH)/Creep.hpp $(CODEPATH)/Creep.cpp
$(CC) $(CFLAGS) $(CODEPATH)/Creep.cpp
mv Creep.o $(OBJPATH)/
$(OBJPATH)/Food.o : $(CODEPATH)/Food.hpp $(CODEPATH)/Food.cpp
$(CC) $(CFLAGS) $(CODEPATH)/Food.cpp
mv Food.o $(OBJPATH)/
$(OBJPATH)/Brick.o : $(CODEPATH)/Brick.hpp $(CODEPATH)/Brick.cpp
$(CC) $(CFLAGS) $(CODEPATH)/Brick.cpp
mv Brick.o $(OBJPATH)/
#This archive is the final result of the compilation:
World.a : $(OBJ)
ar rvs World.a $(OBJ)
cp $(CODEPATH)/World.hpp . #I need both the World.a file and the World.hpp file from code/ for this library to function.
#Delete all object files and the archive:
clean :
rm $(OBJPATH)/*.o World.a World.hpp *~ $(CODEPATH)/*~
#Delete all backup files made by Gedit:
pretty :
rm *~ $(CODEPATH)/*~
What this basically does is compiles all the .o files in the folder object/, and then puts them in a file named World.a. Then it just copies over World.hpp, because that's the library's header file. I believe that a lot of this code can be minimized so it's more readable and generic (doesn't require me to edit it each time I make a new class).

Look at the rule for one object file:
$(OBJPATH)/World.o : $(CODEPATH)/World.hpp $(CODEPATH)/World.cpp
$(CC) $(CFLAGS) $(CODEPATH)/World.cpp
mv World.o $(OBJPATH)/
Let's build the object where we want it, instead of using mv:
$(OBJPATH)/World.o : $(CODEPATH)/World.hpp $(CODEPATH)/World.cpp
$(CC) $(CFLAGS) $(CODEPATH)/World.cpp -o $(OBJPATH)/World.o
then use an automatic variable:
$(OBJPATH)/World.o : $(CODEPATH)/World.hpp $(CODEPATH)/World.cpp
$(CC) $(CFLAGS) $(CODEPATH)/World.cpp -o $#
then reverse the order of the prerequisites, so that we can use another automatic variable:
$(OBJPATH)/World.o : $(CODEPATH)/World.cpp $(CODEPATH)/World.hpp
$(CC) $(CFLAGS) $< -o $#
Now the command doesn't mention World by name, so we could use the same rule for all the objects. To make this answer short I'll first make it a static pattern rule:
$(OBJPATH)/World.o : $(OBJPATH)/%.o : $(CODEPATH)/%.cpp $(CODEPATH)/%.hpp
$(CC) $(CFLAGS) $< -o $#
then combine them all:
OBJ=$(OBJPATH)/World.o $(OBJPATH)/Block.o $(OBJPATH)/Creep.o $(OBJPATH)/Food.o $(OBJPATH)/Brick.o
$(OBJ) : $(OBJPATH)/%.o : $(CODEPATH)/%.cpp $(CODEPATH)/%.hpp
$(CC) $(CFLAGS) $< -o $#
Now when you want to add a new file, all you have to do is add it to the OBJ=... line. There are a few more improvements you can make, but this is enough for one day.

Related

GNU Make reports no rule when dealing with a target under subdirectory with source from another directory

My project's directory is mounted via NFS. From the directory under which it is mounted, I call make -f msh/Makefile cd=msh. (msh is my mount.) cd is a variable in the Makefile that is prepended to source files. This works fine with source files directly under cd. However, if the source files are under a subdirectory within cd, Make fails, saying that there is no rule to make that target. It does not fail if I call Make from within my mount.
This is my Makefile.
CC?=gcc
CFLAGS:=-Wall -Werror -D_POSIX_C_SOURCE=200112L $(CFLAGS)
cd?=.
objects_nix=if/tty.o
objects:=sub.o if.o $(objects_nix)
ifdef SO
CFLAGS+=-fPIC
bin=libmsh.so
else
bin=libmsh.a
endif
.PHONY : clean
$(bin) :
libmsh.a : $(objects)
$(AR) -r -c -s $# $(objects)
libmsh.so : $(objects)
#echo
#echo If you have resumed compilation after not having used the SO flag,
#echo you should run make clean.
#echo
$(LD) $(LDFLAGS) -shared -o $# $(objects)
test : $(cd)/test.c $(bin)
ifdef SO
$(CC) $(CFLAGS) -I$(cd) $(LDFLAGS) -L. -lmsh -Wl,-rpath,. -o $# $(cd)/test.c
else
$(CC) $(CFLAGS) -I$(cd) $(LDFLAGS) -o $# $(cd)/test.c $(bin)
endif
%.o : $(cd)/%.c
$(CC) $(CFLAGS) -c -o $# $<
clean :
rm -f libmsh.so libmsh.a
rm -f $(objects)
rm -f test.o test
I have tried creating another rule for the subdirectory, and this works. But I'd like it to work with only the one rule.
You have told Make how to make a .o file from .c file in $(cd). It does not know how to make a .o file if the .c file in some other directory. You can solve this in various ways, such as:
Add an explicit rule for all directories. You have already done that.
Use VPATH.
Create a Makefile for each directory.

GNU make pattern rule when .c files in different directory

I can write pattern rules like that to compile .cfiles to .ofiles.
%.o:%.c
$(CC) -c $< $(CFLAGS) -o $#
But it seems that this method will only work when all the c file are in the same directory.
If my project's struct is like this
|-folder1
|----a.c
|----b.c
|-folder2
|----c.c
|----d.c
|Makefile
I have to change my Makefile to this
%.o:folder1/%.c
$(CC) -c $< $(CFLAGS) -o $#
%.o:folder2/%.c
$(CC) -c $< $(CFLAGS) -o $#
If i have a lot of folders, I think repeating code like this is not the correct way to solve the problem.
Anyone has better solutions?

How to move .o on project folder?

I wrote this Makefile to move all .o of the project inside a directory 'obj' in the main folder.
Directories
.:
actor/ lib/ Controller.cpp Controller.h Controller.o doc.txt main.cpp main.o Makefile uno VRP*
./actor:
Customer.cpp Customer.h Customer.o Depot.cpp Depot.h Depot.o Route.cpp Route.h Route.o Vehicle.cpp Vehicle.h Vehicle.o
./lib:
Search.cpp Search.h Search.o Utils.cpp Utils.h Utils.o VRP.cpp VRP.h VRP.o
Makefile
CXX=g++
RM=rm -rf
BIN_NAME=VRP
CPPFLAGS=-s -O2 -std=gnu++11 -Wall
SRCS=$(wildcard *.cpp actor/*.cpp lib/*.cpp)
OBJS=$(subst .cpp,.o,$(SRCS))
all: $(OBJS_DIR) $(BIN_NAME)
$(OBJS_DIR):
mkdir $(OBJS_DIR)
$OBJS_DIR)/%.o : $(SRCS)
$(CXX) $(CPPFLAGS) -c $< -o $#
$(BIN_NAME) : $(OBJS)
$(CXX) -o $# $^
debug:
$(CXX) -g $(CPPFLAGS) -o $(BIN_NAME) $(OBJS)
.PHONY : all clean
clean:
$(RM) $(OBJS) $(OBJS_DIR)
dist-clean: clean
$(RM) $(BIN_NAME)
How can I make it works?
This line $OBJS_DIR)/%.o : $(SRCS) sets the prerequisites of every file that matches $OBJS_DIR)/%.o to all the files in $(SRCS) that's not even close to what you want. (It is also a typo. You are missing the opening ().
You can't write a single rule for what you are trying to do here you need three pattern rules (or one with a vpath/VPATH setup).
$(OBJS_DIR)/%.o: %.cpp
$(CXX) $(CPPFLAGS) -c $< -o $#
$(OBJS_DIR)/%.o: actor/%.cpp
$(CXX) $(CPPFLAGS) -c $< -o $#
$(OBJS_DIR)/%.o: lib/%.cpp
$(CXX) $(CPPFLAGS) -c $< -o $#
That being said you don't actually have any targets that match $(OBJS_DIR)/%.o since the value of $(OBJS) is Controller.o ... actor/Customer.o ... lib/Search.o. To fix that you also need:
OBJS=$(addprefix $(OBJS_DIR)/,$(patsubst %.cpp,%.o,$(notdir $(SRCS))))
$(notdir) to get just the filename from the source files.
$(patsubst) instead of $(subst) just for correctness (subst would have modified a Bar.cpp.cpp file to Bar.o.o).
$(addprefix) to add the $(OBJS_DIR) prefix to the bare object file names.

multiple targets build in makefile

Any idea why something like this wouldnt work in makefile ?
all : $(GOAL_DB) $(GOAL)
%.d: %.cpp
$(CC) $(CPPFLAGS_DB) $< > $#
%.o : %.cpp
$(CC) $(FLAGS_DB) $< -o $#
$(GOAL_DB) : $(OFILES)
$(CC) $(LFLAGS_DB) -o $# $^ $(LIBS_DB)
strip $(GOAL_DB)
rm -f *.o *.d
%.d: %.cpp
$(CC) $(CPPFLAGS) $< > $#
%.o : %.cpp
$(CC) $(FLAGS) $< -o $#
$(GOAL) : $(OFILES)
$(CC) $(LFLAGS) -o $# $^ $(LIBS)
strip $(GOAL)
rm -f *.o *.d
I'm just trying to build two different targets using make all , GNU make.
The first target builds fine , but it not creating new objects files for another target.
A makefile is not like a standard program that is executed sequentially. It seems you've made the assumption that new rules appearing before a new target will apply to that target. This is not the case. The makefile is fully evaluated for variables, targets, dependencies, and more, before it starts applying rules.
Make is going to match those $(OFILES) against only one of those %.d: targets, probably the first target pattern it finds.
The reason you are not getting new objects for the other target is that to make it looks like you are building the same set of files twice, thus skipping the second build because it's already complete.
A solution is to use 'target specific variables':
all : $(GOAL_DB) $(GOAL)
$(GOAL): BUILD_FLAGS=$(FLAGS)
$(GOAL): BUILD_CPPFLAGS=$(CPPFLAGS)
$(GOAL): BUILD_OUTDIR=./outdir
$(GOAL): $(OFILES)
$(GOAL_DB): BUILD_FLAGS=$(FLAGS_DB)
$(GOAL_DB): BUILD_CPPFLAGS=$(CPPFLAGS_DB)
$(GOAL_DB): BUILD_OUTDIR=./outdir_db
$(GOAL_DB): $(OFILES)
%.d: %.cpp
mkdir -p $(BUILD_OUTDIR)
$(CC) $(BUILD_CPPFLAGS) $< > $(BUILD_OUTDIR)/$#
%.o : %.cpp
mkdir -p $(BUILD_OUTDIR)
$(CC) $(BUILD_FLAGS) $< -o $(BUILD_OUTDIR)/$#

Want to place all .o files into a directory, but make stops after compilng fist one

I want to have a neat makefile containing explicit dependencies but placing all .o objects in a separate directory to link it altogether later (in an another file).
The problem is that my make stops after compiling the first source and then stops with no error whatsoever.
CC=gcc
CFLAGS=-c -Wall -pedantic -std=c99
DIR=../obj
$(DIR)/CList.o : CList.c CList.h CList_aux.h Observation.h CList_View_aux.h
$(CC) $(CFLAGS) CList.c -o $#
$(DIR)/CList_aux.o : CList_aux.c CList.h CNode.h
$(CC) $(CFLAGS) CList_aux.c -o $#
$(DIR)/CList_View_aux.o : CList_View_aux.c CNode.h Observation.h
$(CC) $(CFLAGS) CList_View_aux.c -o $#
$(DIR)/CNode.o : CNode.c CNode.h CNode_aux.h Observation.h CList.h
$(CC) $(CFLAGS) CNode.c -o $#
$(DIR)/CNode_aux.o : CNode_aux.c CNode.h Observation.h
$(CC) $(CFLAGS) CNode_aux.c -o $#
$(DIR)/Observation.o : Observation.c Observation.h Observation_aux.h CNode.h
$(CC) $(CFLAGS) Observation.c -o $#
$(DIR)/Observation_aux.o : Observation.c Observation.h
$(CC) $(CFLAGS) Observation_aux.c -o $#
$(DIR)/Record.o : Record.c Record.h Observation.h
$(CC) $(CFLAGS) Record.c -o $#
By default, make builds the first target in the makefile. In this case, that is ${DIR}/CList.o.
You need a different first target, conventionally called all:
OBJECTS = \
$(DIR)/CList.o \
$(DIR)/CList_aux.o \
$(DIR)/CList_View_aux.o \
$(DIR)/CNode.o \
$(DIR)/CNode_aux.o \
$(DIR)/Observation.o \
$(DIR)/Observation_aux.o
all: ${OBJECTS}
Note that this works whether there are any object files in the ${DIR} or not; a wildcard looking for object files in the directory makes sure that those that have already been compiled once are up to date, but doesn't try building those which failed to compile previously, or simply aren't there.
If the Makefile is really just as much as you posted, then you're missing the all: rule. Without having an explicit all rule, make assumes that the first present rule is to be made, so it stops after that. In order to achieve what you want, add (append) this to the Makefile (change the final executable name respectively):
OBJECTS = $(wildcard $(DIR)/*.o)
all: $(EXECUTABLE)
$(EXECUTABLE): $(OBJECTS)
$(LD) $(LDFLAGS) -o $# $^

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