I like to use the g++ -MM feature to auto-build my dependencies. The way I do this is as follows:
include $(ALLOBJ:%.o=%.d)
%.d: %.cxx
#echo making dependencies for $<
#g++ -MM $(CXXFLAGS) $< -o $#
#sed -i 's,$*\.o,& $# ,g' $#
Basically I can give this rule ALLOBJ, and it will:
convert every .o name to a .d name, and include it,
when it can't find a .d, it will create it from the .cxx file
the final line of the %.d: %.cxx rule will add the name of the .d file to the file itself, so that the dependency will be updated automatically.
The issue arises when I remove a header: the .d file still expects to find it, and make will get upset when it's not there. One solution is to replace include with -include, and to build the dependencies within the compile rule. Unfortunately this requires a dependency generation line for each compile rule, and will also ignore all other include errors (which seems risky). Is there some other simple way to auto-build dependencies which avoids this issue?
Reading the g++ manual a bit more, and thanks to #jackKelly and #Beta's responses above, I found the following solution:
include $(ALLOBJ:%.o=%.d)
%.d: %.cxx
#echo making dependencies for $<
#g++ -MM -MP -MT $*.d -MT $*.o $(CXXFLAGS) $< -o $#
To summarize the flags:
-MM: build dependencies (rather than compiling)
-MP: build 'dummy' targets for all headers. This prevents make from complaining when headers are deleted and thus can't be found.
-MT: specify the targets for the rule. This allows us to tell make the .d file depends on the headers without resorting to the ugly sed rule.
I don't believe my solution is any more correct than #Beta's solution. I tend to use multiple compile rules for C++ files in the same makefile, so having a single dependency rule for all of them is slightly cleaner (in my case) than generating the dependencies in each compile rule.
To restate my answer to the other question, I do it this way:
%.o: %.cpp
#echo making $# and dependencies for $< at the same time
#$(CC) -MD -c $(CXXFLAGS) -o $# $<
#cp $*.d $*.P
#sed -e 's/#.*//' -e 's/^[^:]*: *//' -e 's/ *\\$$//' \
-e '/^$$/ d' -e 's/$$/ :/' < $*.P >> $*.d
#rm $*.P
-include $(ALLOBJ:%.o=%.d)
EDIT:
It... It produces the dependency file, but more cleanly and without the sed command:
%.o: %.cpp
#echo making $# and dependencies for $< at the same time
#$(CC) -c $(CXXFLAGS) -o $# $<
#$(CC) -MM -MP $(CXXFLAGS) $< -o $*.d
-include *.d
So now I have to modify the %.o rule in my own makefiles. From now on there'll be a little bit of #JackKelly in everything I compile, mocking me. Oh, this is a black day.
Related
I have several lines in Makefile that are compiling and producing .o and .d files. I want two sets of .o .d to be produced, something like:
name.d
name_hello.d
name.o
name_hello.o
Already found how to change names of .d using "$(#:.o=_hello.d)" but have no success changing .o Perhaps i need to play with $# but have no idea how to do it.
Here is Make file code:
$(OBJECT_DIRECTORY)/%.o: %.c
# Build header dependencies
$(CC) $(CFLAGS) $(INCLUDEPATHS) -M $< -MF "$(#:.o=.d)" -MT $#
$(CC) $(CFLAGS) $(INCLUDEPATHS) -M $< -MF "$(#:.o=_hello.d)" -MT $#
# Do the actual compilation
$(CC) $(CFLAGS) $(INCLUDEPATHS) -c -o $# $<
$(CC) $(CFLAGS) $(INCLUDEPATHS) -c -o $# $< - this line i want to change
I use arm-none-eabi-gcc.exe for ARMs and make.exe
Update
Seems that using separate target is preffered solution than changing names. So, i did separate target for it. But it is never used. In other place of the Makefile there is next line of code that tells compiler what .o files to use:
C_OBJECTS = $(addprefix $(OBJECT_DIRECTORY)/, $(C_SOURCE_FILENAMES:.c=.o) )
I suppose that i need to change it to something like:
C_OBJECTS_hello = $(addprefix $(OBJECT_DIRECTORY)/, $(C_SOURCE_FILENAMES:.c=*_hello.o) )
Please tell how to modify C_OBJECTS in order to make compiler use *_hello.o files
Update 2
This is how C_OBJECTS used, i suppose some kind of a filter in C_OBJECTS tells CC ( arm-none-eabi-gcc.exe ) to use certain .o files. And since *_hello.o files are not used in the filter they are also not produced in their target.
## Link C and assembler objects to an .out file
$(OUTPUT_BINARY_DIRECTORY)/$(OUTPUT_FILENAME).out: $(BUILD_DIRECTORIES) $(C_OBJECTS) $(ASSEMBLER_OBJECTS) $(LIBRARIES)
$(CC) $(LDFLAGS) $(C_OBJECTS) $(ASSEMBLER_OBJECTS) $(LIBRARIES) -o $(OUTPUT_BINARY_DIRECTORY)/$(OUTPUT_FILENAME).out
I know that this is written in make help and i am reading it, but still not able to find an answer
Update 3
Here is how i modified 'C_OBJECTS' , and seems this works:
C_OBJECTS_hello = $(addprefix $(OBJECT_DIRECTORY)/, $(C_SOURCE_FILENAMES:.c=_hello.o) )
You indeed would use a replacement. The $# variable expands all the %.o matches. That's why you had a $(#:.o=.d) replacement; you needed a .d file for each %.o match.
In this case, you can indeed use a $(#:.o=_hello.o) replacement. Note that this is NOT a dependency of the %.c input; it is a secondary output.
The alternative is to add a second output $(OBJECT_DIRECTORY)/%.o $(OBJECT_DIRECTORY)/%_hello.o: %.c. In this case, you wouldn't use $# but use $* which is the matched %. So your two dependency files would be $(OBJECT_DIRECTORY)/$*.d and $(OBJECT_DIRECTORY)/$*_hello.d
Your makefile rule produces more files than make is aware of. $(OBJECT_DIRECTORY)/%.o: %.c says it builds one .o from .c, whereas you would like it to build 4 files.
You need to make make aware what files its rules produces, so that it can build a complete dependency graph:
$(OBJECT_DIRECTORY)/%.o $(OBJECT_DIRECTORY)/%.d: %.c # Compile and build dependencies.
$(CC) -c -o $# $(CFLAGS) $(INCLUDEPATHS) -MD -MP $<
$(OBJECT_DIRECTORY)/%_hello.o $(OBJECT_DIRECTORY)/%_hello.d: %.c # Compile and build dependencies.
$(CC) -c -o $# $(CFLAGS) $(INCLUDEPATHS) -MD -MP $<
Note that these rules do not explicitly name the .d output file, letting the compiler determine it by replacing .o with .d.
Now that you have two rules instead of one make can parallelize their execution when -j flag is used.
Note that you should not need explicit rules for auto-generated dependencies for the reasons stated in https://stackoverflow.com/a/7358961/412080.
I'm trying to write an etags target in make based on the dependency information generated by gcc. Is there some way of getting at all the dependencies in one go? Or, failing that, how would I write a rule that is only executed when the "tags" target is made and that passes all the source and header files to etags? I only want to index the files actually compiled (including headers). I'm aware that I can sed around in the .d files myself but I'm trying to find a more elegant and less brittle solution.
I have the following (excerpt)
DEPFILES = $(OBJFILES:.o=.d)
%.o : %.c
#echo "Compiling $<"
$(NO_ECHO) $(CC) $(CFLAGS) -MMD -MF $(#:.o=.d) -o $# -c $<
%.o : %.S
#echo "Compiling $<"
$(NO_ECHO) $(CC) $(ASFLAGS) -MMD -MF $(#:.o=.d) -o $# -c $<
$(TARGET) : $(OBJFILES)
#echo "Linking $#"
$(NO_ECHO) $(LD) $(LDFLAGS) -o $# $(OBJFILES) $(LIBS:%=-l%)
.PHONY: clean
# Order-only dependency to make Dep/obj-directories if they are not
# present
$(OBJFILES) : | $(ALLPATHS)
$(ALLPATHS):
$(NO_ECHO) mkdir -p $(ALLPATHS)
# Depend on the makefiles
$(OBJFILES) : $(SRC_PATH)/Makefile $(MAKECFG) $(BUILDCFG)
# Include dependency files
sinclude $(DEPFILES)
Edit : The following seems to work but I'd really like to find a more elegant solution
(the double sort/uniq is just for performance).
tags : $(TARGET)
cat $(DEPFILES) | sort | uniq | sed 's/.*:.*$$//' | tr -d '\\' | tr "\n" " " | xargs -n 1 readlink -f | sort | uniq | xargs etags -a
I came here looking for an answer to the same thing as the original question, but went away as didn't think it was adequately answered and found a solution that doesn't require sed etc.
Below I assume a Makefile similar to the Makefile in the original question which generates dep files using the compiler and includes them.
For the compiling rule where the .d files are generated, I modified the compiler options to ask it to also make the tags target depend on the dependancies of the object file. I added -MQ $# -MQ tags to the options. These options explicitly tell the compiler the names of the target for the dependancies.
%.o : %.c
$(CC) $(CFLAGS) -MMD -MF $(#:.o=.d) -o $# -c $< -MQ $# -MQ tags
Now we don't need to explicitly give the tags target a list of dependencies, it will be generated when we compile and will be updated accordingly as the source files change. In my case I am using ctags and this is what the options are I used it with:
tags:
ctags $^ -o $#
The $^ variable is the list of dependancies. This will be a list of source and header files as each .d file will look something like this:
main.o tags: main.c a.h b.h
Hope that helps.
You need to create a mini tag file for each .d file and then use that to update your etags file. Note this appends stuff to the file, rather than removing and replacing, so you might need to remote the tags file occasionally (ctags has a --update option)
TAGFILES = $(OBJFILES:.o=.t)
# prune the .d files a bit to get a list of files for etags to scan
%.t: %.d
cat $< | sed stuff > $#
cat $# | etags -a $#
.PHONY: tags
tags: $(TAGFILES)
I want to use the include directive only for a specific target. I do not want to run the other makefiles when the target is not needed because it means the makefiles are generated needlessly.
So is there a way to conditionally use the include directive, which is conditional on a target? Or somehow to make the include directive a prerequisite of a target.
Here's what I have so far:
# Flags
INCDIR = $(CURDIR)/include
CFLAGS = -Wall -Wno-overflow -Wno-uninitialized -pedantic -std=c99 -I$(INCDIR) -O3
LFLAGS = -flat_namespace -dynamiclib -undefined dynamic_lookup
# Directory names
# Set vpath search paths
vpath %.h include
vpath %.c src
vpath %.o build
vpath %.d build
# Get files for the core library
CORE_FILES = $(wildcard src/*.c)
CORE_OBJS = $(patsubst src/%.c, build/%.o, $(CORE_FILES))
CORE_DEPS = $(CORE_OBJS:.o=.d)
# Core library target linking
core : $(CORE_OBJS) | bin
$(CC) $(LFLAGS) -o bin/libcbitcoin.2.0.dylib $(CORE_OBJS)
# Include header prerequisites (How to do only for "core" target?)
include $(CORE_DEPS)
# Makefiles for header dependencies.
$(CORE_DEPS): build/%.d: src/%.c | build
rm -f $#; \
$(CC) -I$(INCDIR) -MM $< -MT '$(#:.d=.o) $#' > $#
# Objects depend on directory
$(CORE_OBS) : | build
# Create build directory
build:
mkdir build
# Create bin directory
bin:
mkdir bin
# Core Compilation
$(CORE_OBJS): build/%.o: src/%.c
$(CC) -c $(CFLAGS) $< -o $#
# Depencies require include/CBDependencies.h as a prerequisite
build/CBOpenSSLCrypto.o: include/CBDependencies.h
# Crypto library target linking
crypto : build/CBOpenSSLCrypto.o -lcrypto -lssl | bin
$(CC) $(LFLAGS) -o bin/libcbitcoin-crypto.2.0.dylib build/CBOpenSSLCrypto.o -lcrypto -lssl
# Crypto library compile
build/CBOpenSSLCrypto.o: dependencies/crypto/CBOpenSSLCrypto.c
$(CC) -c $(CFLAGS) $< -o $#
#Clean
clean:
rm -f $(CORE_OBJS) $(CORE_DEPS) build/CBOpenSSLCrypto.o
As you should be able to tell I do not need to include the ".d" files for "crypto" but I do for "core" (default goal).
Thank you for any help.
Make is not a procedural language, so treating it as one goes against the grain; your makefiles will be difficult to scale, and it can lead to subtle bugs.
There's a better way by Tom Tromey that's clean, efficient and scalable. The trick is to realize that you can build the dependency file in the same step as the object file. The dependencies simply tell Make when the object is due to be rebuilt; you don't need them when you first build the object, because Make knows that the object must be built. And if the dependencies change, that can only be because something in the source or the old dependencies has changed, so again Make knows that the object must be rebuilt. (This is not obvious, so it may take a little cogitation.)
$(CORE_OBJS): build/%.o: src/%.c
$(CC) -c $(CFLAGS) $< -o $#
$(CC) -MM -MF build/$*.d $<
-include build/*.d
There's one more hitch: if you alter the code so as to remove a dependency -- and also remove that file -- you won't be able to rebuild, because the old dependency list will still demand a file which can no longer be found. The sophisticated solution is to process the dependency file so as to make each prerequisite (e.g. header) a target in its own right, with no commands, so that it can be assumed to be rebuilt when needed:
$(CORE_OBJS): build/%.o: src/%.c
$(CC) -c $(CFLAGS) $< -o $#
$(CC) -MM -MF build/$*.d $<
#cp build/$*.d build/$*.P
#sed -e 's/#.*//' -e 's/^[^:]*: *//' -e 's/ *\\$$//' \
-e '/^$$/ d' -e 's/$$/ :/' < build/$*.P >> build/$*.d;
#rm build/$*.P
A cruder method, but almost as foolproof, is to put in catch-all rules for headers and sources:
$(CORE_OBJS): build/%.o: src/%.c
$(CC) -c $(CFLAGS) $< -o $#
$(CC) -MM -MF build/$*.d $<
%.cc %.h:
EDIT:
To break down the new commands:
The -MM option tells gcc to produce a make rule for the object file, instead of preprocessing or compiling. The default is to send the rule to wherever it would send preprocessed output, which will usually be stdout.
The -MF option, used with -MM, specifies the output file. So -MM -MF build/$*.d will put the rule where we want it.
So the following two commands are (almost always) equivalent:
$(CC) -MM -MF build/$*.d $<
$(CC) -MM $< > build/$*.d
(I've left out the -I$(...) and the possibility of using the -MMD option, because both get a little complicated and are not really the point of the question.)
You can use MAKECMDGOALS.
ifeq (core,$(MAKECMDGOALS))
include $(CORE_DEPS)
endif
You could of course, use ifneq (,$(findstring core,$(MAKECMDGOALS))) if there was a possibility of more than one target.
Note: this is a 'quick and dirty' solution -- I agree with Beta that you shouldn't make this a common practice (this could get messy if you did it in a lot of makefiles...).
John
I can't help breaking the guidelines for what is a good answer.
My answer to the original question is in my opinion, no you cannot include rules that are dependant on the target -all rules are processed before targets are considered. This is a limitation of make (I guess). Then again, good point, there is MAKECMDGOALS, but is this not just a hack in the make utility itself?
The answer from Beta is reasonable and orthodox enough, but you can't call it clean even if it is the best that can be done. It won't work if make has not processed the particular target before and the appropriate build/*.d dependency file is not sitting there.
I'm reading Managing Projects with GNU Make, and found this example in Chapter 2.7 - Automatic Dependency Generation. The Author says their from the GNU manual:
%.d: %c
$(CC) -M $(CPPFLAGS $< > $#.$$$$; \
sed s',\($*\)\.o[ :]*,\1.o $# : ,g' < $#.$$$$ > $#; \
rm -f $#.$$$$
However, I was able to do the same thing with this (note the sed):
-include $(subst .c,.d,$(SOURCES))
%.d: %.c
#$(CC) -M $(CPPFLAGS) $< | sed 's|:| $*.d : |' > $#;
All these lines do is generate the dependencies, then add in the *.d name. They had to change the first line from:
foo.o: bar.h foo.h fubar.h
to
foo.o foo.d : bar.h foo.h fubar.h
Mine is simpler and seems to work quite well, but I assume that the GNU folks had a reason for their sed command. Also:
Why do a redirect of the file into sed? Why not simply take it as a commond line parameter
Why not skip the intermediary file completely?
I know the guys at GNU could have thought of these too, but for some reason, went with the more complex setup. I just want to understand their reasoning, so I can do these on the fly.
Actually even the rule itself is not necessary. There is a great overview of different approaches of generating Make-style dependencies in Advanced Auto-Dependency Generation article written by Paul D. Smith.
After all, the following rule should be enough (in case of using GCC):
%.o: %.c
$(CC) $(CPPFLAGS) $(CFLAGS) -MMD -MP -o $# -c $<
-include $(SOURCES:.c=.d)
UPD.
I have also answered a similar question a bit earlier. It contains an explanation (quotation of GCC manual) of -MMD -MP options.
Addressing the question: Why do a redirect of the file into sed? If you do:
#$(CC) -M $(CPPFLAGS) $< | sed 's|:| $*.d : |' > $#;
and the compilation fails (errors out and generates no output), you will create an empty target file. When make is run again, it will see the newly created empty file and not regenerate it, leading to build errors. Using intermediate files is a common defensive strategy to avoid accidentally created an empty target.
An even simpler solution is to get rid of the sed call completely, as gcc can do everything you need directly:
%.d: %.c
$(CC) -M $(CPPFLAGS) -MF $# $< -MT "$*.o $#"
Here is a simple header file for six different programs. This Makefile used to work just fine, but then I changed the programs to include other implementation files. This Makefile needs to get changed so that if the implementation files change the files that include those implementation files get recompiled.
all: load list show add delete btree
%: %.cpp
g++ $< -g -o $#
You can use the -MM option of gcc to create dependency files, and then include those into your Makefile.
TARGETS = load list show add delete btree
all: $(TARGETS)
%: %.cpp
g++ $< -g -o $# -MM -MF $#.dd
sed "s/$#\.o:/$#:/" $#.dd > $#.d
-#rm $#.dd
DEPS=$(TARGETS:%=%.d)
-include $(DEPS)
The sed line is present to change the dependency file from load.o: load.c to load: load.c.