I own a Digilent Nexys2 and I'm coding in VHDL, using Xilinx ISE ide.
I have to generate a very specific clock for my purpose, using the onboard DCM:
starting from a base clock of 50MHz, duty cycle = 50%, I need a 78MHz, duty cycle = 70%, output clock.
The main problem is that I didn't noticed any option to control the output duty cycle or other related things using the wizard. Am I missing something? Is there any solution or work around?
thanks in advance for your help
IMHO, it's not possible with the Spartan 3E (DCM). With other components, e.g. the Kintex7 with the MMCME2_ADV, it is possible.
Related
I've been working on a DPR project for quite some time, and I've been wondering if there's a way to electrically disable FPGA regions in order to lower the static power consumption of the chip?
Using Xilinx Vivado, I know I'm able to define pblocks and tell the toolchain not to place any block/route in those, but since the region is still powered I think there will still be some leakage current in here; hence not reducing static power consumption.
Given my understanding of an FPGA architecture, I suppose there may be a way to disable entire clock regions, but I can't tell for sure. Vivado documentations don't seem to point at a way of doing so.
Also, given the hypothesis that this can be done, would ICAP still be functionning and available for DPR purpose? In my opinion, if one would try to reconfigure an FPGA using ICAP on a disabled region, this would just do nothing on the FPGA part, but I fear this would left the ICAP hanging.
Has any of you found a way to do this, or is there a piece of documenation that I'm missing on?
Have a nice day.
There is no way how to power down a part of a Xilinx FPGA (to reduce its static power), as far as I know.
You can still do a clock gating (to switch off the clock ticking) to reduce a dynamic power, which is usually the bigger portion of the overall power budget.
See for example the BUFGCE primitive in the UltraScale(+) architecture, which can enable/disable a clock feeding a specific region (chapter "BUFGCE Clock Buffers" on the page 29 of the UG572 (v1.10.1) "UltraScale Architecture Clocking Resources").
Any of you have any material about this?
I want to show an std_logic_vector(0 to 29) on the osciloscope
That's 30 bits ... you don't want to probe 30 pins.
I'd use 2 spare pins and roll a simple serial interface off a suitable (e.g. 1 MHz) clock and a /32 counter.
One pin shifts out each bit according to the count, the other is set when you send the first bit, as a convenient triggering signal.
Either let it free run, or tell it to start (inside the FPGA) every time you update that signal.
Most FPGA vendors provide some kind of in-system debugger (like ChipScope for Xilinx ISE designs). These provide a very powerful debugging perspective for your FPGA design and allow you to record waveforms on hundreds of signals.
I am trying to learn VHDL, an am writing a simple transmitter for serial data. However, I encountered a problem - I need a clock to run it, and the datasheet for my FPGA (MAX II) says this:
Output of the internal oscillator for MAX II devices: 3.3-5.5 MHz
So there is no way to reliably set the frequency of the internal FPGA oscillator? And if there is, how do you do it efficiently?
Thanks!
No, there is no way to set the frequency of the internal oscillator. It's most likely an RC oscillator built into the die, so its frequency will depend heavily on silicon process variations and temperature.
If you need something more precise, it'll need to be external to the CPLD.
I am designing a processor using an Altera DE1 kit.
I will be running test bench to stress the processor.
I want to know if there is any way to measure only the power consumption of my design and neglecting the other power dissipation caused by the DE1 board.
TIA for the answer.
Measure power at an idle state. The idle state can be many things. This needs to be decided by you:
The board operating when the FPGA is not programmed (no bitstream loaded).
FPGA loaded, but you hold down the reset for the logic.
Place the FPGA in some kind of suspended state (sleep mode).
Now that you have your reference power measurement, measure the power with your design running fully. Subtract one from the other, and you will have a result which is close to what you are searching for (The board may consume differently, at each idle state, than it would have been when running normally with your design).
You should be able to replace the 0-Ohm resistor R29 by a shunt resistor and measure the core current of the fpga through that. It's right in series with VCCINT so it should reflect only the current used by the fpga logic.
There's also R30 in series with VCCIO, if you want to include IO power consumption as well.
The resistor names are from this schematic (the only one I could find so far): http://d1.amobbs.com/bbs_upload782111/files_33/ourdev_586508CWZW3R.pdf
I am writing a code using VHDL to convert 24MHz and 12 MHz clock to 8 MHz clock. Can anyone please help me in this coding? Thanks in advance.
Is this for an FPGA? Or something else? Are you really dividing a clock, or just a signal? For a divide by three counter, try this link:
http://www.asic-world.com/examples/vhdl/divide_by_3.html
And for a 2/3:
http://www.edaboard.com/thread42620.html
As Martin has already said, use a clock management device by Xilinx recommendations in order to divide your clock down to a lower rate.
While you might be tempted to implement a clock divider using logic and a counter, you will not obtain good synthesis results.
Here are some tips:
Be sure to closely read and follow recommendations for the clock management hardware for your device. There can be quite a few "gotchas" related to power-up, reset, loss of clock lock, etc.
Make sure that you are operating the clock management device within its specifications. See your device's datasheet for more information (in this case for the S3-A).
Use FPGA Editor to verify correct placement and configuration of your clock management units (i.e. did it end up in the right spot on the chip)
Adhere to recommended practices for feedback clocks, and clock buffering.
Use a DCM or PLL (depending on the family of FPGA) - there's examples in the documentation. If you tell us which family, I might be able to point you more directly.
EDIT:
As you say Spartan 3ADSP - you need to either:
Use the Core Generator Clocking Wizard to create you a VHDL or Verilog file with the components you need in and hope you never need to understand what's going on
Read the libraries guide and the DCM section of the Userguide for that chip and instantiate a DCM on your own and apply the correct generics/parameters to it.
Don't forget to apply a reset pulse to the DCM after configuration has finished 0 and make sure that pulse lasts long enough. The min pulse length is different for each family, I don't recall off the top of my head what it is for that chip, so check the datasheet.