I am supposed to write a Makefile for a project I need to do. I have it all done but when I try to do it, I get the following output:
make: Nothing to be done for `Makefile'
What might be the cause of this?
Here's my Makefile file:
###########################################################
# Makefile for XXXXX
# name1, name2
# account1, account2
###########################################################
EXEC = a1
CC = /opt/SUNWspro/bin/cc
$(EXEC):
$(CC) -o $(EXEC) a1.cpp a1.h a1.sic
rm -f *.o
clean:
rm -f *.o core diss $(EXEC)
#######################[ EOF: Makefile ]###################
Edit:
Thanks to a kind user, I now know what happened.
Now I have the following output
/opt/SUNWspro/bin/cc -o a1 a1.cpp a1.h a1.sic
ld: fatal: file a1.cpp: unknown file type
ld: fatal: file processing errors. No output written to a1
make: *** [a1] Error 2
Can you please help?
Are you typing make Makefile for some reason? Don't. Just type make. make a1 or make -f Makefile will work for your situation, too, but why bother with the extra typing?
As an aside, it's a bit weird to include header files on your compile line. Also, your makefile doesn't specify any dependencies, which is kind of the whole reason to have one in the first place...
Edit: to answer your new question, don't compile C++ code with a C compiler. That said, I'm not sure about the link error you're getting. Is a1.cpp not a normal source file (type file a1.cpp to find out)?
It seems like you are having very fundamental problems. Maybe starting with a good beginner book would be useful?
Related
I am supposed to write a Makefile for a project I need to do. I have it all done but when I try to do it, I get the following output:
make: Nothing to be done for `Makefile'
What might be the cause of this?
Here's my Makefile file:
###########################################################
# Makefile for XXXXX
# name1, name2
# account1, account2
###########################################################
EXEC = a1
CC = /opt/SUNWspro/bin/cc
$(EXEC):
$(CC) -o $(EXEC) a1.cpp a1.h a1.sic
rm -f *.o
clean:
rm -f *.o core diss $(EXEC)
#######################[ EOF: Makefile ]###################
Edit:
Thanks to a kind user, I now know what happened.
Now I have the following output
/opt/SUNWspro/bin/cc -o a1 a1.cpp a1.h a1.sic
ld: fatal: file a1.cpp: unknown file type
ld: fatal: file processing errors. No output written to a1
make: *** [a1] Error 2
Can you please help?
Are you typing make Makefile for some reason? Don't. Just type make. make a1 or make -f Makefile will work for your situation, too, but why bother with the extra typing?
As an aside, it's a bit weird to include header files on your compile line. Also, your makefile doesn't specify any dependencies, which is kind of the whole reason to have one in the first place...
Edit: to answer your new question, don't compile C++ code with a C compiler. That said, I'm not sure about the link error you're getting. Is a1.cpp not a normal source file (type file a1.cpp to find out)?
It seems like you are having very fundamental problems. Maybe starting with a good beginner book would be useful?
I have searched for hours for an answer to this. I am new to gcc and Makefiles.
I have a Makefile in some source code that looks like this:
CC=gcc
SRCDIR=src
BINDIR=../bin
CFLAGS= -flag
LIBS= -lthing
...
$(BINDIR)/program_name: $(SRCDIR)/program_name.c
$(CC) $(CFLAGS) $(SRCDIR)/program_name.c -o $(BINDIR)/program_name $(LIBS)
I understand what all of this means except what ../ in BINDIR is meant to do. When I make the Makefile, I get the error message:
/usr/bin/ld: cannot open output file ../bin/program_name: No such file or directory
collect2: error: ld returned 1 exit status
Makefile:20: recipe for target '../bin/program_name' failed
make: *** [../bin/program_name] Error 1
My guess is that the original author of this Makefile meant that the bin folder should go in the parent directory of where the Makefile is located. I know when using the Linux CLI command cd that the dot dot means go up a directory. Is that what this is trying to achieve?
To automatically create the $(BINDIR) directory before it is actually needed you must declare it as a prerequisite (dependence) of any target that uses it. But each time its content changes its timestamp also changes. So, declaring it as a regular prerequisite is not the best thing to do because the targets depending on it would be re-built without real reason, just because the content of $(BINDIR) changed.
This is why make also supports order-only prerequisites (OOPs):
$(BINDIR)/program_name: $(SRCDIR)/program_name.c | $(BINDIR)
$(CC) $(CFLAGS) $< -o $# $(LIBS)
$(BINDIR):
mkdir -p $#
Note the | that introduces the list of OOPs. An OOP is built if it does not exist, which causes the targets depending on it to be (re-)built too. But if it exists make does not even consider its last modification time. Even if some target depending on it is older, it is not rebuilt just because of that.
Note: I also used the $< and $# automatic variables. In the rule's recipe they expand as the first prerequisite ($(SRCDIR)/program_name.c) and the target ($(BINDIR)/program_name), respectively. They are highly recommended: less typing, less errors prone, more generic rules... they have many good properties.
Your makefile is missing a rule to create the BINDIR directory - if it doesn't exist, your link line won't be able to put the resulting binary there! A rule like this one should do it:
$(BINDIR):
mkdir -p $(BINDIR)
Just make sure that any other rules (like the one in your question) also depend on this directory!
i have been trying to make a correct makefile for a while now but i keep getting the error "make: *** No rule to make target `all'. Stop."
i have one main program: mpasswdsort.c
and the c file wich is used by mpasswdsort, it comes with a header as well:
list.c and list.h
my makefile:
CC=gcc
CFLAGS=-Wall -pedantic -ansi
all: mpasswdsort
server: mpasswdsort.o list.o
$(CC) mpasswdsort.o list.o -o mpasswdsort
mpasswdsort.o: mpasswdsort.cpp
$(CC) $(CFLAGS) mpasswdsort.cpp
list.o: list.cpp
$(CC) $(CFLAGS) list.cpp
clean:
rm -f server client *.o core
I am unsure if its wrong in the makefile or if the makefil isnt supposed to be a .txt file.
The error message you present indicates that make does not see any rule for building target "all". It is exactly the same diagnostic that GNU make emits when there is no makefile at all. Since the makefile contents you present do contain a rule for target "all", I conclude that make is not seeing them.
That may be because the makefile is in a different directory, because its name is different from the ones make tries by default (Makefile or makefile is conventional; GNU's version of make also checks for GNUmakefile), or because an access-control issue prevents make from reading the file. Since you remark
I am unsure if its wrong in the makefile or if the makefil isnt
supposed to be a .txt file.
, the most likely conclusion is that (at least) the filename is wrong. Makefiles are text files, but text file names don't necessarily end with ".txt". In fact, on Linux and other UNIXes, most of them don't. Makefiles shouldn't have such an extension, though, technically, you can use the -f option to tell make the name of the makefile to use.
For me, quite simply, I was initiating the make init command outside of the target directory that I wished to create the makefile. Hope this helps someone.
I'm using a MAC so renaming the "MakeFile" to "Makefile" did the trick for me.
And one more thing, I got this error after fixing the previous one:
Makefile:3: *** missing separator. Stop.
Replacing the four spaces with tabs solved this problem for me! Simply just delete the space before the commands in your "Makefile" and put a tab behind them.
Although Make is working fine but by default it only compiling those files that have been changed, even when I run make all. It say like Nothing to Do.
One scenario where I neeed to compile all the files is when I change something in a header file which is being accessed in multiple .c files. But make does not recognize it until I open any .c file any save & quit again.
Makefile contents can be seen in this post :
Questions about Makefile - what is "$+" & where are .c files/dependencies called here ?
Although this is also a problem but actual problem I want to discuss here is something different.
In order to compile all files what I did was that I ran make clean which indeed removed all object files and then I ran make again but this time it gives an error :-
....
mec/gen_crc32table > mec/crc32table.h
mec/gen_crc32table: 1: mec/gen_crc32table: Syntax error: end of file unexpected
(expecting ")")
make: *** [mec/crc32table.h] Error 2
I checked contents of crc32table.h but file is empty. So, I copy crc32table.h from my backup of previous code and now its running successfully. Now I run make clean and 'make' again to check it but this time it is working fine.
I do not know what the mystery here ?
I guess these lines are doing something which I am not able to understand ? Please help me on this.
crc32.o: mec/crc32table.h mec/crc32.c
$(CC) -o $# -c -I. $(CFLAGS) mec/crc32.c
mec/crc32table.h: mec/gen_crc32table
mec/gen_crc32table > mec/crc32table.h
The issue is this snippet:
mec/crc32table.h: mec/gen_crc32table
mec/gen_crc32table > mec/crc32table.h
Ask yourself "What happens if the gen_crc32table command exits with an error?" Make stops (good) but leaves behind a corrupt crc32table.h (bad). Two choices: (i) re-write gen_crc32table so that it accepts a -o parameter; (ii) shell trickery.
(i)
mec/crc32table.h: mec/gen_crc32table
mec/gen_crc32table -o mec/crc32table.h
(ii)
mec/crc32table.h: mec/gen_crc32table
mec/gen_crc32table >temp-file-with-an-obscure-name
mv temp-file-with-an-obscure-name $#
The mv will not happen if gen_crc32table errors.
All,
I'm trying to pass variables to make from the command line. My command is below
make ARCH=arm CROSS_COMPILE=/my_dir/bin/arm-openwrt-linux-g++
The error I received is
g++: error: arm: No such file or directory
But the file 'arm-openwrt-linux-g++' does exist.
I think the problem is I need to pass varibale to sub-make files. Can some help with an example of how to pass varialbes to sub-makefile from the command-line. I have tried using the -e and export options for make, but can't seen to get anything to work.
Thanks
Content of makefile:
# GNU Make solution makefile autogenerated by Premake
# Type "make help" for usage help
ifndef config
config=debug
endif
export config
PROJECTS := json openjaus
.PHONY: all clean help $(PROJECTS)
all: $(PROJECTS)
json:
#echo "==== Building json ($(config)) ===="
#${MAKE} --no-print-directory -C .build -f json.make
openjaus: json
#echo "==== Building openjaus ($(config)) ===="
#${MAKE} --no-print-directory -C .build -f openjaus.make
So, your problem is not related to sending variables over the command line.
Your problem is that in one of the makefiles in your sub-directories, which you haven't shown us, you're using the variable $(ARCH) in an incorrect way such that the expansion of the command line is not a legal g++ command line.
Based on the error message, most likely you're adding a space somewhere where it shouldn't be, so instead of something like -fmarch=arm you're getting -fmarch= arm. Obviously this is just an example because you didn't provide nearly enough information.
One other note: we can't know how your makefiles work but typically makefiles that support a variable like CROSS_COMPILE expect it to be set to just the prefix of the cross-compilation command; in your case it would be CROSS_COMPILE=/my_dir/bin/arm-openwrt-linux-. But, your makefiles might be different.
When asking questions, it's best to if you don't immediately jump to a guess about what the answer is. First describe the problem, and that includes showing the error line as well as a few lines before it. For example in this case you're getting an error from g++ so the command line that make printed out showing you how it invoked g++ would have helped greatly.
Once you've given the underlying detail, then if you think you have an idea about what the problem is go ahead and suggest it, and/or ask about it.
If you provide the rule that invokes g++ and/or the output from make showing the g++ command line, then we can help more.
Cheers!
Here's what I think needs to happen:
You need to make sure that your sub-makefiles actually respect the $(ARCH) and $(CROSS_COMPILE) variables. Are they also generated by Premake? If so, is that how it handles cross-compilation? Check the docs.
In my test (below), I found that variables set on the command line are propagated to sub-makes, which makes me think that your sub-makefiles aren't respecting $(ARCH):
Makefile:
a:
$(MAKE) -C z
z/Makefile:
a:
#echo "MAKE=$(MAKE)"
#echo "ARCH=$(ARCH)"
Running make with no arguments:
$ make
make -C z
make[1]: Entering directory `/home/foo/test/z'
MAKE=make
ARCH=
make[1]: Leaving directory `/home/foo/test/z'
Running make ARCH=bar:
$ make ARCH=bar
make -C z
make[1]: Entering directory `/home/foo/z/z'
MAKE=make
ARCH=bar
make[1]: Leaving directory `/home/foo/z/z'