How can I make this VHDL code synthesizable? - vhdl

Question

I have VHDL code that uses havily the fallowing syntax:
signal_1 <= (others => '0') when cau_state = st_idle else
signal_2 - signal_3 when cau_state = st_cycle_1 else
signal_4 when cau_state = st_cycle_2 else
signal_5 when cau_state = st_cycle_3 else
signal_6 when cau_state = st_cycle_4 else
signal_1;
Where cau_state is a signal that holds the current state. This syntax worked in simulation on Model-Sim and everything worked fine. But when I wanted to burn the code to an FPGA, the code didn't synthesize on Altera Quartus II 32-bit ver. 12.1 And I got the fallowing error messages:
Warning (13012): Latch CAU:uut|cross_3_sig[0][31] has unsafe behavior
Warning (13013): Ports D and ENA on the latch are fed by the same signal CAU:uut|cau_state.st_cycle_2
Warning (13012): Latch CAU:uut|cross_3_sig[0][30] has unsafe behavior
Warning (13013): Ports D and ENA on the latch are fed by the same signal CAU:uut|cau_state.st_cycle_2
I get these messages for many signals, but NOT for all the signals that are using this syntax. And for a signal that get this message I get it for all its bits: cross_3_sig[0][31] to cross_3_sig[0][0]. The syntax for the signal cross_3_sig(0) is:
constant WIDTH : integer := 32;
...
subtype scalar is std_logic_vector((WIDTH-1) downto 0);
type vector_nd is array (natural range <>) of scalar;
subtype vector_3d is vector_nd(2 downto 0);
...
signal cross_3_sig : vector_3d;
...
cross_3_sig(0) <= sum_mults_out_sig when cau_state = st_cycle_2 else
mult1_out_sig - mult2_out_sig when cau_state = st_cycle_9 else
cross_3_sig(0);
And there are some places where I assign cross_3_sig(0) into other signals, i.e.:
numer_sig <= C_ZERO - cross_3_sig(0) & (16 downto 0 => '0');
mult1_in2_sig <= (others => '0') when cau_state = st_idle else
...
cross_3_sig(0) when cau_state = st_cycle_11 else
...
What is the problem, and how can I fix it?

Answer 1

The problem is that this form of expression creates a latch (which is sensitive to glitches on its control signal) and furthermore it is a latch with multiple control signals, for which there is no direct equivalent in real hardware.
signal_1 <= (others => '0') when cau_state = st_idle else
...
signal_6 when cau_state = st_cycle_4 else
signal_1;
Any time you see (outside a clocked process) something like
signal_1 <= ... else signal_1;
you know you have a problem. This is a signal feeding itself directly, an attempt to use a simple wire as a memory.
The correct use for this pattern is as a multiplexer, not as memory,
output_1 <= input_1 when ... else
input_2 when ... else
input_n;
The correct way to remember the old value of signal1 is a clocked process, e.g.
process (clk)
begin
if rising_edge(clk) then
if cau_state = st_idle then signal_1 <= (others => '0')
...
elsif cau_state = st_cycle_4 then signal_1 <= signal_6;
end if;
end if;
end process;
With no assignment, signal_1 will maintain its current value.
Or a better alternative : use a case statement in the process:
process (clk)
begin
if rising_edge(clk) then
case cau_state is
when st_idle => signal_1 <= (others => '0')
...
when st_cycle_4 => signal_1 <= signal_6;
-- when others => some default action
end case;
end if;
end process;
This does change the semantics to a clocked design, but unclocked designs are troublesome in FPGA, to say the least!