VHDL - How to add 1 to STD_LOGIC_VECTOR? [closed] - vhdl

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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
-- use ieee.std_logic_arith.all;
-- use ieee.numeric_std.all;
-- entity part contain R for output of Register
entity register_16 is
port( input: in std_logic_vector(15 downto 0);
ld, inc, clk, clr: in std_logic;
R: buffer std_logic_vector(15 downto 0));
end register_16 ;
-- it have to parallel process
architecture behavioral of register_16 is
begin
reg: process (input, ld, clk, clr)
variable R_temp: std_logic_vector(15 downto 0);
begin
if (clr = '1') then
R_temp := b"0000000000000000";
elsif (clk'event and clk = '1') then
if (ld = '1') then
R_temp := input;
end if;
end if;
R <= R_temp;
end process reg;
-- my error in this step
inc_R: process (inc)
begin
R <= R + '1';
end process inc_R;
end behavioral;
Main process (reg) works correctly, but other process has error adding 1.

Answer 1

You will have to convert the vector to an integer an back again, here's an example:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
signal in : std_logic_vector( 7 downto 0 );
signal out : std_logic_vector( 7 downto 0 );
out <= std_logic_vector(to_unsigned(to_integer(unsigned( in )) + 1, 8));
For a good picture about type conversion take a look here:
http://www.bitweenie.com/listings/vhdl-type-conversion/

Answer 2

Sorry to say, but there are quite a lot of things wrong with your code...
You are mixing combinatorial and sequential code in the same process, which is poor coding style. If coded correctly, there really is no need for the variable R_temp.
The sensitivity list is a simulation aid only, yet you are trying to use it as a conditional (when inc changes, increment R). This will not work in hardware. When starting out with VHDL, my suggestion is to use VHDL_2008 and always use process(all) as the sensitivity list. This avoids beginner errors, since it reflects what synthesis does.
You are creating a combinatorial loop in the second process. This will not show up in simulation because of 2. above, but will cause errors in synthesis.
As already mentioned by baldyHDL, you are assigning to R in multiple processes.
Prefer unsigned to std_logic_vector when dealing with numbers. Generally you should not include std_logic_arith, nor std_logic_unsigned, just std_logic_1164 and numeric_std.
Adding a std_logic value (such as '1') is not standard, or at least not supported by all tools. Simply use an integer instead: R <= R + 1;
By your code, I gather that you are trying to write a counter with increment, load and clear signals. I don't just want to give you the code (that would ruin the learning experience for you), but try to fit the entire counter into a single process, using the following template:
process(clk) begin
if(rising_edge(clk)) then
-- Your code here vvv
if(clr = '1') then
elsif(ld = '1') then
elsif(inc = '1') then
end if;
-- Your code here ^^^
end if;
end process;

Answer 3

you write R in both of your processes. this leads to a multi-driver situation that is not possible to synthesise. to solve it, combine the processes, e.g.:
reg: process (clk, clr)
variable R_temp : std_logic_vector(15 downto 0);
begin
if (clr='1') then
R_temp := b"0000000000000000";
elsif (clk'event and clk='1') then
if (ld='1') then
R_temp := input;
elsif (inc='1') then
R_temp := R_temp + '1';
end if;
end if;
R <= R_temp;
end process reg;

Answer 4

You should be able to add a vector containing the value 1 as this, as you are using the numeric_std library:
R <= R + x"0001";

Answer 5

I used the following libraries and it was able to do something similar
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
...
signal cnt : std_logic_vector(3 downto 0);
begin
process(clk, reset, ce, cnt)
begin
if(reset = '1') then
cnt <= "0000";
elsif(clk'event and clk='1') then
if(ce='1') then
if(cnt = "1001") then
cnt <= "0000";
else
cnt <= cnt + 1;