I have just updated make to
GNU Make 3.82
Built for x86_64-pc-linux-gnu
Copyright (C) 2010 Free Software Foundation, Inc.
License GPLv3+: GNU GPL version 3 or later <http://gnu.org/licenses/gpl.html>
This is free software: you are free to change and redistribute it.
There is NO WARRANTY, to the extent permitted by law.
and before hand this make file worked
MODULE_NAME = module
$(MODULE_NAME)-objs := Charset.o Connector.o Fpga.o FpgaBus.o FpgaFlash.o I2c.o Key.o Module.o \
Oled.o PhoneAudio.o Splash.o AudioCodecIO.o Connection.o Server.o
EXTRA_CFLAGS=-I./include2 -I./include -DALLOW_LOWER_CASE
ifneq ($(KERNELRELEASE),)
obj-m := $(MODULE_NAME).o
else
KDIR := ./build/
PWD := $(shell pwd)
all:
ARCH=arm CROSS_COMPILE=/usr/bin/arm-softfloat-linux-uclibceabi- $(MAKE) -C $(KDIR) M=$(PWD) modules
clean:
ARCH=arm CROSS_COMPILE=/usr/bin/arm-softfloat-linux-uclibceabi- $(MAKE) -C $(KDIR) M=$(PWD) clean
install:
ARCH=arm CROSS_COMPILE=/usr/bin/arm-softfloat-linux-uclibceabi- $(MAKE) -C $(KDIR) M=$(PWD) modules_install
endif
now it does not with this error
ARCH=arm CROSS_COMPILE=/usr/bin/arm-softfloat-linux-uclibceabi- make -C ./build/ M=/home/liam/Dev/driver modules
Makefile:23: *** mixed implicit and normal rules. Stop.
make[1]: Entering directory `/home/shared/firmware/atmel/kernel'
make: *** [all] Error 2
make[1]: Leaving directory `/home/shared/firmware/atmel/kernel'
Any idea what is causing this issue?
EDIT:
Ok, i have more info now. An auto generated Makefile is pulled in from the ./build/ directory and looks like this.
# Automatically generated by /home/shared/firmware/src/linux/scripts/mkmakefile: don't edit
VERSION = 2
PATCHLEVEL = 6
lastword = $(word $(words $(1)),$(1))
makedir := $(dir $(call lastword,$(MAKEFILE_LIST)))
MAKEARGS := -C /home/shared/firmware/src/linux
MAKEARGS += O=$(if $(patsubst /%,,$(makedir)),$(CURDIR)/)$(patsubst %/,%,$(makedir))
MAKEFLAGS += --no-print-directory
.PHONY: all $(MAKECMDGOALS)
all := $(filter-out all Makefile,$(MAKECMDGOALS))
all:
$(MAKE) $(MAKEARGS) $(all)
Makefile:;
$(all) %/: all
#:
Looking at it and looking at other posts, this may now be a duplicate question. the last few lines should not be this with this version of make
The fix is changing the kernel build generated Makefile lines
From:
$(all) %/: all
#:
To:
$(all) : all
There are other answers that can explain the reasons behind this better then I can.
Related
So I'm trying to write this makefile and I'm having some issues getting it working, in fact I'm having issues getting makefiles in general working (no doubt due to user error).
make output:
$ make -v
GNU Make 4.2.1
Built for x86_64-unknown-linux-gnu
Copyright (C) 1988-2016 Free Software Foundation, Inc.
License GPLv3+: GNU GPL version 3 or later <http://gnu.org/licenses/gpl.html>
This is free software: you are free to change and redistribute it.
There is NO WARRANTY, to the extent permitted by law.
$ make clean all
rm -rf a.out bin
rm -rf obj
g++ -lm -o bin/a.out
/usr/lib/gcc/x86_64-pc-linux-gnu/8.1.0/../../../../lib/Scrt1.o: In function `_start':
(.text+0x20): undefined reference to `main'
collect2: error: ld returned 1 exit status
make: *** [makefile:32: bin/a.out] Error 1
makefile:
CXX := g++
LXX := g++
CXXFLAGS := -m64 -std=gnu++14 -fno-enforce-eh-specs -fno-rtti -fpermissive -O3 -funswitch-loops -w
CXXDEBUG := -ggdb3 -pg
LDFLAGS := -lm
EXE := a.out
SRC_DIR := src
BIN_DIR := bin
OBJ_DIR := obj
INCLUDE := $(addprefix -I, include)
SOURCES := $(foreach sdir, $(SRC_DIR), $(wildcard $(sdir)/*.cpp))
OBJECTS := $(pathsubst src/%.cpp, obj/%.o, $(SOURCES))
vpath %.cpp $(SRC_DIR)/
define make-goal
$1/%.o: %.cpp
$(CXX) $(INCLUDE) $(CXXFLAGS) -c $$< -o $$#
endef
.PHONY: clean all checkdirs $(BIN_DIR)/a.out
.SECONDARY:
default: all
all: checkdirs $(BIN_DIR)/a.out
$(BIN_DIR)/a.out: $(OBJECTS)
$(LXX) $(LDFLAGS) $^ -o $#
checkdirs: $(BIN_DIR) $(OBJ_DIR)
$(BIN_DIR):
#mkdir -p $#
$(OBJ_DIR):
#mkdir -p $#
clean:
rm -rf $(EXE) $(OBJECTS) bin
#find . -name "*~" -exec rm {} \;
#find . -name "*.o" -exec rm {} \;
rm -rf obj
$(foreach odir,$(OBJ_DIR),$(eval $(call make-goal,$(odir))))
My theory is that the $(foreach ...) at the end is never executed OR that the implicit pattern rules created are not executed (come to think of it I could never get %.o: %.c rules working either)
But honestly? I have no idea, the manual didn't provide any help - at least not that I could find (or, possibly, understand).
What I do understand is that no object files are output, ergo ld fails because it's not finding a main function.
This much is obvious and (painfully) clear to me. (I'm testing this with a very simple example: hello world, it compiles cleanly and executes as expected with g++ world.cpp -o a.out so it's not a g++ sanity issue I think).
Am I using GNU extensions wrong? I know call is a GNU extension.
the expected output would be:
├── bin
│ └── a.out
├── makefile
├── obj
│ └── world.o
└── src
└── world.cpp
This makefile is very similiar to other makefiles I've seen floating around on SO, e.g https://stackoverflow.com/a/2484343/2717116 - however this makefile when copied verbatim also does not appear to work for me - verbatim output:
make all
g++ -o build/test.exe
g++: fatal error: no input files
compilation terminated.
as expected the same issue is faced, namely that make-goal is never reached for one reason or another.
This is wrong:
OBJECTS := $(pathsubst src/%.cpp, obj/%.o, $(SOURCES))
The function name is patsubst not pathsubst.
I have these files main.c, fun.c, and fun.h. I want to use makefile script to run instead of traditional compiling approach. The one who posted the following makefile script said this script will automatically capture the file names in the same directory, so all I need is to navigate to the project directory and write in the terminal $ make. I created a file makefile and put the following script:
TARGET = prog
LIBS = -lm
CC = gcc
CFLAGS = -g -Wall
.PHONY: default all clean
default: $(TARGET)
all: default
OBJECTS = $(patsubst %.c, %.o, $(wildcard *.c))
HEADERS = $(wildcard *.h)
%.o: %.c $(HEADERS)
$(CC) $(CFLAGS) -c $< -o $#
.PRECIOUS: $(TARGET) $(OBJECTS)
$(TARGET): $(OBJECTS)
$(CC) $(OBJECTS) -Wall $(LIBS) -o $#
clean:
-rm -f *.o
-rm -f $(TARGET)
However, I get this error:
make: *** No rule to make targetdefault'. Stop.`
I tried $make -v and got:
GNU Make 3.81
Copyright (C) 2006 Free Software Foundation, Inc.
This is free software; see the source for copying conditions.
There is NO warranty; not even for MERCHANTABILITY or FITNESS FOR A
PARTICULAR PURPOSE.
This program built for i386-apple-darwin11.3.0
I think I misunderstood him! Kindly, what is missing here? Thank you
The missing separator error is because you're not using tabs for the "recipe".
For instance, your TARGET target has a prerequisite of $(OBJECTS), once Make knows that is there (or Makes it) then it will continue to the recipe.
$(TARGET): $(PREREQUISITES)
->(TAB) $(RECIPE)
I have Kernel module sources (for arm) and I would like to compile two different drivers from the same source.
The kernel in compiled with 2 source files and with cross compile.
MODULE_MAME = modulename
SRCS = drv/source.c lib/libsrc.c
OBJS = $(SRCS:.c=.o)
obj-m += $(MODULE_MAME).o
$(MODULE_MAME)-y = $(OBJS)
KDIR := /mykermelsources/
PWD := $(shell pwd)
all:
$(MAKE) -C $(KDIR) ARCH=arm M=$(PWD) modules
clean:
$(MAKE) -C $(KDIR) ARCH=arm M=$(PWD) clean
In one command, I would like to compile 2 modules.
Two choices:
Keeping 3 different Makefiles, one main that will call both other makefiles. One problem with this, I cannot make it working. make -f makefilediff or make --makefile=makefilediff give me an error.
Log:
make -C /mykermelsources/ ARCH=arm M=/home/mychardriver/ modules
make[1]: Entering directory '/mykermelsources'
scripts/Makefile.build:44: /home/mychardriver/Makefile: No such file or directory
make[2]: *** No rule to make target '/home/mychardriver//Makefile'. Stop.
make[1]: *** [_module_/home/mychardriver/] Error 2
make[1]: Leaving directory '/mykermelsources'
make: *** [all] Error 2
Transmitting command line parameter but it doesn't work. make SIDE=1
Seems the SIDE parameter/variable is never transmitted.
ifeq ($(SIDE),1)
MODULE_MAME = modulename_11
else
MODULE_MAME = modulename_22
endif
SRCS = drv/source.c lib/libsrc.c
OBJS = $(SRCS:.c=.o)a
obj-m += $(MODULE_MAME).o
$(MODULE_MAME)-y = $(OBJS)
KDIR := /mykermelsources/
PWD := $(shell pwd)
all:
$(MAKE) -C $(KDIR) ARCH=arm M=$(PWD) SIDE=$(SIDE) modules
clean:
$(MAKE) -C $(KDIR) ARCH=arm M=$(PWD) clean
How can I build 2 kernel modules from same multiple source files ?
Just faced this issue, and this is what I did:
For each moduleX you want to build, write a Kbuild_moduleX with the targets. Example:
obj-$(MODULE) += MODULE.o
MODULE-y := source.o
Then, in your Makefile_moduleX, do:
all:
cp Kbuild_moduleX Kbuild
make -C /lib/modules/$(shell uname -r)/build M=$(shell pwd) modules
rm Kbuild
This works because the kernel scripts will give Kbuild priority over reading Makefile.
To compile, do make -f Makefile_moduleX
Is it pretty? No. Does it work? Yes.
obj-m += hello.0
KDIR = /usr/src/linux-headers-3.16.0-34-generic
all :
$(MAKE) -C $(KDIR) SUBDIRS=$(PWD) modules
clean:
rm -rf *.o
error is: Makefile:9: *** missing separator. Stop.
You can use the below Makefile to build the kernel module. Comments inlined in the Makefile
There is an extra space before $(MAKE) in your makefile
obj-m = hello.o
KDIR = /usr/src/linux-headers-3.16.0-34-generic
# Here the commands to build the target should start in the next line with a tab space
all:
<TAB>make -C $(KDIR) M=$(PWD) modules
clean:
<TAB>make -C $(KDIR) M=$(PWD) clean
I'm writing a character driver to sit on top of a modified version of ahci in the source tree. I basically have something that looks like this:
topdir
|
|- Makfile
|
|- mod_ahci
| | - Makefile, codefiles
|
|- char_interface
| | - Makefile, codefiles
now, char_interface requires symbols from mod_ahci. I have the appropriate EXPORT_SYMBOL() macro use for the symbols I need to export. However, I'm having trouble getting the makefiles right to pick up the header file in mod_ahci from char_interface. My toplevel Makefile
ifneq ($(KERNELRELEASE),)
obj-y := mod_ahci/ char_interface/
else
KERNELDIR ?= /lib/modules/$(shell uname -r)/build
PWD := $(shell pwd)
default:
$(MAKE) -C $(KERNELDIR) M=$(PWD) modules
modules_install:
$(MAKE) -C $(KERNELDIR) M=$(PWD) modules_install
endif
The makefile for char_interface (because the other builds just fine)
ifneq ($(KERNELRELEASE),)
ccflags-y += -I../mod_ahci
obj-m := char_interface.o
else
KERNELDIR ?= /lib/modules/$(shell uname -r)/build
default:
$(MAKE) -C $(KERNELDIR) M=$(shell pwd) modules
modules_install:
$(MAKE) -C $(KERNELDIR) M=$(shell pwd) modules_install
endif
clean:
-sudo rmmod ahcip
-rm -f *.ko* *.mod.* *.o modules.order Modules.symvers
I have referenced various text files in the kernel documentation. For example, I'm referring to .../Documentation/kbuild/makefiles.txt right now as well as .../Documentation/kbuild/modules.txt. Whenever I build, I'm getting /home/captaink/devel/kmodtests/char_interface/char_interface.c:2:22: error: mod_ahci.h: No such file or directory. There is a file named mod_ahci.h in the directory ../mod_ahci. What am I getting wrong with my use of ccflags-y in the makefile for the char driver?
Thanks
After some digging, I found the answer to the problem. I was misunderstanding what was happening with the makefile's that I was viewing from LDD3 and the kernel documentation (which is, apparently, exactly where O'Reilly took their examples). The build system actually changes directories into /usr/src/kernels/$(uname -r)/build (or similar) because this is why my header file wasn't being found by the compiler.
I'm not saying this is an elegant way of doing this, but here's how I fixed it. The makefile in the top directory now looks like:
ifneq ($(KERNELRELEASE),)
obj-y := mod_ahci/ char_interface/
else
KERNELDIR ?= /lib/modules/$(shell uname -r)/build
PWD := $(shell pwd)
default:
$(MAKE) -C $(KERNELDIR) M=$(PWD) TOP_DIR=$(PWD) modules
modules_install:
$(MAKE) -C $(KERNELDIR) M=$(PWD) modules_install
endif
And the makefile in the subdirectory containing the char driver interface looks like:
ifneq ($(KERNELRELEASE),)
ccflags-y += -I$(TOP_DIR)/mod_ahci
obj-m := char_interface.o
else
KERNELDIR ?= /lib/modules/$(shell uname -r)/build
default:
$(MAKE) -C $(KERNELDIR) M=$(shell pwd) modules
modules_install:
$(MAKE) -C $(KERNELDIR) M=$(shell pwd) modules_install
endif
clean:
-sudo rmmod ahcip
-rm -f *.ko* *.mod.* *.o modules.order Modules.symvers
As you can tell, the makefiles have been copied extensively. The subdirectories probably don't need the "shared" makefile stuff in them because that's taken care of by the higher level makefile. Nevertheless, the modules now build and the character driver I have knows of the exported symbols I made in my modified ahci driver.
I hope this may help someone who's a neophyte, like myself, to the Linux kernel build world and Linux kernel drivers.