I have the following problem: I have to implement 8 bit left shifter that makes one shift to left, the code of it is:
entity left_shift is
generic ( N: integer := 8);
Port(
Databitsin : in STD_LOGIC_vector(N-1 downto 0);
Databitsout : out STD_LOGIC_vector(N-1 downto 0);
Carry: out std_logic
);
end left_shift;
architecture Behavioral_l of left_shift is
begin
Databitsout(N-1 downto 1)<= Databitsin(N-2 downto 0);
Carry<=Databitsin(N-1);
end Behavioral_l;
then i have to implement another one that has to make one shift to the right
entity Right_shift is
generic ( N: integer := 8);
Port(
Databitsin : in STD_LOGIC_vector(N-1 downto 0);
Databitsout : out STD_LOGIC_vector(N-1 downto 0);
Carry: out std_logic
);
end Right_shift;
architecture Behavioral of Right_shift is
begin
Databitsout(N-2 downto 0)<= Databitsin(N-1 downto 1);
Carry<=Databitsin(0);
end Behavioral;
Now, I have to build a main Module which has to use these 2 components to make cyclically shift (left,right).
How can I do that?
there's different ways to implement cyclical shift (=rotate!). if you add a direction-selector Dir, you can have both directions within one code.
ex.1
add "use IEEE.NUMERIC_STD.all" to make use of numeric_std package functions:
Databitsout<=std_logic_vector(rotate_right(unsigned(Databitsin),1)) when Dir='0' else
std_logic_vector(rotate_left(unsigned(Databitsin),1));
ex. 2
use std_logic_vectors directly:
Databitsout<=Databitsin(0) & Databitsin(N-1 downto 1) when Dir='0' else
Databitsin(N-2 downto 0) & Databitsin(N-1);
carry flag is the same in both:
Carry<= Databitsin(0) when Dir='0' else
Databitsin(N-1);
This sounds a lot like homework, but never-the-less:
Firstly, why do you have to use two components? The elegant solution is to write one component capable of shifting left or right.
If you have some astoundingly good reason to do things the way you've suggested, try instantiating both and multiplexing between the databitsout signals of both depending on the desired diection. To make a cyclic shift instead of a linear one, you need to concatinate the carry bit into the appropriate end of the logic vector array.
Related
Image of the DUT
I'm trying to write an internal nibble transmission guarded by a parity bit.
For this I want to write a transmitter/receiver logic which is shown in the image attached.
So I have a 4 bit input vector and generate a parity bit for it and here comes my problem.
I want to attach the parity bit to the input vector. But the input vector is only 4 bit. Is there a way to resize it by simply attaching the parity bit to the input vector or do i have to transmit the parity bit seperately?
And as a little side question in relation to the whole implementation:
Do I have to create seperated processes for the receiver and transmitter like I have in my code or do I simply have to write one process containing both?
My first idea was to simply use an internal vector with 5 bit to attach the parity bit but the problem is that I only want the given input as output in the end and there is the same problem. In the process of the parity checker I have to fill the output vector which is 4 bit with the intern 5 bit vector and have no idea if this simply works like I tried in my code.
I hope you can understand the problem.
Thanks.
architecture rtl of odd parity is
signal rxdat_s : out std_logic_vector(3 downto 0);
signal ok_s : out std_logic;
signal txdat_s : in std_logic_vector(3 downto 0);
signal secured_s : std_logic_vector (4 downto 0);
begin
odd_parity_gen: process ( txdat_s, clk ) is
variable txdat_v : std_logic_vector(3 downto 0);
variable secured_v : std_logic_vector(4 downto 0);
variable odd_parity_v : integer;
begin
txdat_v := txdat_s;
odd_parity_v := xnor txdat_v;
secured_v := txdat_v + odd_parity_v;
secured_s <= secured_v;
end process odd_parity_gen;
odd_parity_check: process () is
variable ok_v : integer;
variable rxdat_v : std_logic_vector(3 downto 0);
variable secured_v : std_logic_vector(4 downto 0);
begin
rxdat_v := rxdat_s;
secured_v := secured_s;
ok_v := ok_s;
ok_v := xnor secured_v;
rxdat_v := secured_v;
ok_s <= ok_v;
rxdat_s <= rxdat_v;
reg: process ( clk ) is
begin
if rising_edge (clk) then
if nres = '0' then
--reset all signals
else
--main logic
end if;
end if;
end process;
I assume this code has been cobbled together as example. You have input/output ports in an architecture and your ports are rather confusing: rxdat_s is an output and txdat_s is an input. Also you have no 5 bit output port which you need to send 4 bits plus parity.
Also this: secured_v := txdat_v + odd_parity_v; adds a an integer and a std_logic_vector which requires conversion or a library.
Assuming your parity generator is correct you can add a parity bit to the front using concatenation: the & operator.
secured_s <= odd_parity_v & rxdat_s;
Or at the back using:
secured_s <= rxdat_s & odd_parity_v;
If I needed to perform a bitwise AND operation of two 16bit inputs and obtain a 16bit output in VHDL, would I be able to just AND the two inputs and store the result as the output vector? Or would I need to loop through each bit of the inputs, AND them, then store the result in the output vector? Would this work similarly for operations like or and xor?
The "and" operator is overloaded in the std_logic_1164 package for std_logic, std_ulogic, std_logic_vector, and std_ulogic_vector (the types typically used). It is also defined for bit and bit_vector (as well as signed and unsigned).
So it is as straightforward as just applying the "and"operator. For example:
architecture rtl of test is
signal a : std_logic_vector(15 downto 0);
signal b : std_logic_vector(15 downto 0);
signal y : std_logic_vector(15 downto 0);
begin
y <= a and b; -- Or 'y <= a xor b;' or 'y <= a or b;', etc
end architecture rtl;
You can just use and.
library IEEE;
use IEEE.std_logic_1164.all;
entity and_gate is
port(
a: in std_logic_vector(15 downto 0);
b: in std_logic_vector(15 downto 0);
q: out std_logic_vector(15 downto 0));
end and_gate;
architecture rtl of and_gate is
begin
q <= a and b;
end rtl;
http://www.edaplayground.com/x/Xuw
I am in the process of trying to write some code that will simply just shift a 32 bit vector left or right, with a 5 bit input that will be used for the shift amount (shamt). The issue I am having is trying to convert an std_logic_vector to an integer. My code is this:
library ieee;
use ieee.STD_LOGIC_1164.all;
use ieee.STD_LOGIC_ARITH.all;
entity shiftlogical is
port(x : in std_logic_vector(31 downto 0);
shamt : in std_logic_vector( 4 downto 0);
y : out std_logic_vector(31 downto 0));
end shiftlogical;
architecture beh of shiftlogical is
signal shift : integer;
signal temp : std_logic_vector(31 downto 0);
begin
shift <= conv_integer(unsigned(shamt));
temp <= x(shift downto 0);
y <= temp;
end beh;
The code is not complete I know, but to test some ideas I am trying to pass "00010" (2) into shamt, but shift comes out to be -2147483648. But I cannot figure out why it is doing this, nor can I find any resources online that shows anything different than what I am doing. I greatly appreciate any help.
-2147483648 (-2**31) is the default initial value for integers, being the leftmost, most negative value in its range. It suggests that the signal assignment to shift has not executed. Most likely because it is a continuous assignment and there hasn't been an event on shamt to cause it to update.
std_logic_arith is not an IEEE standard library. You should use to_integer() from ieee.numeric_std instead. It is also beneficial to keep numeric ports as unsigned or signed so that your intent is clear and to minimize type conversions. Also, you cannot directly assign the variable length slice of x to temp since their lengths do not match. You should use resize() (from numeric_std) to extend the length back to 32-bits or rethink your approach.
I fixed the obvious typo in the entity name, started the simulation (ModelSim) and forced the signal shamt to "00010". Then just after trying to run for 1 ps, ModelSim complains about:
Fatal: (vsim-3420) Array lengths do not match. Left is 32 (31 downto 0). Right is 0 (-2147483648 downto 0 (null array)).
Time: 0 ps Iteration: 0 Process: /shiftlogical/line__16 File: shiftlogical.vhdl
Fatal error in Architecture beh at shiftlogical.vhdl line 16
That is because all your concurrent statements are executed in parallel. The new signal values are scheduled for the next delta cycle within the simulation. Thus, the line
temp <= x(shift downto 0);
is executed with the old value of shift which is the initial value of this signal. The initial value of an integer is -2**31 as also Kevin pointed out.
Of course you can initialize the signal shift, but the only value which will not result in an error will be 31 because in this asignment the signal on the left and the expression on the right must match in array (std_logic_vector) size. The signal shamt must be forced to "11111" as well, so that shift keeps 31.
You cannot easily fix this, because for a left shift you must add zeros at the right (LSB) and for a right shift zeros or the sign at the left (MSB).
#Martin Zabel what I had really tested there was to see if shift would hold an integer value which it did until I tried to pass it in for temp <= x(shift downto 0); What I realized was that the signal needed to really be a variable to work as intended and as follows my code consists of:
library ieee;
use ieee.STD_LOGIC_1164.all;
use ieee.STD_LOGIC_ARITH.all;
entity shiftlogical is
port(x: in std_logic_vector(31 downto 0);
shamt: in std_logic_vector(4 downto 0);
dir: in std_logic;
y: out std_logic_vector(31 downto 0));
end shiftlogical;
architecture beh of shiftlogical is
begin
process(dir)
variable shift : integer;
begin
shift := conv_integer(unsigned(shamt));
if(dir = '0') then --Left shift
y(31 downto shift) <= x(31-shift downto 0);
y(shift downto 0) <= (others => '0');
elsif(dir = '1') then --Right shift
y(31-shift downto 0) <= x(31 downto shift);
y(31 downto 31-shift) <= (others => '0');
else --Always left shift
y(31 downto shift) <= x(31-shift downto 0);
y(shift downto 0) <= (others => '0');
end if;
end process;
end beh;
I have four std_logic_vectors (15 downto 0) and want to stack them into a std_logic_vector (63 downt 0) so fare I have found one way of doing it but is it the correct way or is there a more optimal and correct way to do it?
signal slv16_1,slv16_2,slv16_3,slv16_4 : std_logic_vector(15 downto 0);
signal slv64 : std_logic_vector(63 downto 0);
slv64(15 downto 0) <= slv16_1;
slv64(31 downto 16) <= slv16_2;
slv64(47 downto 32) <= slv16_3;
slv64(63 downto 48) <= slv16_4;
An easy way to accomplish this is to use the concatenation operator &. It achieves the same thing you did above, but with less code required.
slv64 <= slv16_4 & slv16_3 & slv16_2 & slv16_1;
Since the source vectors have unique names, I don't see a way to automate this. What you might be able to try is to never use the 16-bit vectors, and instead use slices of the larger 64 bit vector. So instead of an assignment like this:
slv16_1 <= "0101110000111010";
Use
slv64(15 downto 0) <= "0101110000111010";
Or instead of an entity instantiation where you connect slv16_2 like this:
output_port => slv16_2,
Use
output_port => slv64(31 downto 16),
I would really need to see more of your code to understand what might work best, but my basic answer is 'use the larger vector in the first place'.
If you can't do this for some reason, an alternative would be to declare your 16-bit vectors as an array of arrays:
type slv16_array_type is array (integer range <>) of std_logic_vector(15 downto 0);
signal slv16_array : slv16_array_type(3 downto 0);
You could then assign to the elements like this:
slv16_array(0) <= "0101";
You could combine the elements of this type with a generate loop:
slv16_combine : for i in 0 to 3 generate
slv64((16*(i+1))-1 downto 16*i) <= slv16_array(i);
end generate;
VHDL guide says that this one should work:
slv64 <= (slv16_4, slv16_3, slv16_2, slv16_1);
This has me bugging for quite some time, but is it possible to describe entities in VHDL similar to how templates work in C++ (or to lesser extend generics?). Simply leaving the actual port types to be only decided during synthesize/compilation?
An example would be a multiplexer, say I have a 4 input multiplexer, now I have several bus sizes I use this multiplexer for, -4,6,7,8-. Currently I wrote a different multiplexer for each different bus size; however the output is simply one of the chosen inputs forwarded, and is thus of the same type as the bus.
This seems overly redundant and error prone (choose correct multiplexer at correct times, keep them all in line, update them as I change the bus size). Is there no way to parameterize this?
non generic version below to show the idea.
entity mux_6bit_4input is
port ( input_0 : in std_logic_vector (5 downto 0);
input_1 : in std_logic_vector (5 downto 0);
input_2 : in std_logic_vector (5 downto 0);
input_3 : in std_logic_vector (5 downto 0);
sel : in std_logic_vector (1 downto 0);
output : out std_logic_vector (5 downto 0)
);
end entity mux_6bit_4input;
Maybe I misunderstood the question, but doesn't the common solution using generics solve your problem?
library ieee;
use ieee.std_logic_1164.all;
entity mux_4x1 is
generic (
DATA_WIDTH: integer := 8
);
port (
input_0: in std_logic_vector(DATA_WIDTH-1 downto 0);
input_1: in std_logic_vector(DATA_WIDTH-1 downto 0);
input_2: in std_logic_vector(DATA_WIDTH-1 downto 0);
input_3: in std_logic_vector(DATA_WIDTH-1 downto 0);
sel: in std_logic_vector (1 downto 0);
output: out std_logic_vector(DATA_WIDTH-1 downto 0)
);
end;
architecture behavior of mux_4x1 is
begin
output <=
input_0 when sel = "00" else
input_1 when sel = "01" else
input_2 when sel = "10" else
input_3;
end;
Another solution, if you want to keep things really generic, is to use the cool generic types in VHDL-2008. My simulator doesn't yet support this feature, so here's an example from the excellent book VHDL 2008: Just the New Stuff:
entity generic_mux2 is
generic (type data_type);
port (
sel: in bit;
a, b: in data_type;
z: out data_type
);
end;
architecture rtl of mux2 is
begin
z <= a when sel = '0' else b;
end;
Another option is to use unconstrained arrays:
entity mux_4input is
port (
input_0 : in std_logic_vector ;
input_1 : in std_logic_vector ;
input_2 : in std_logic_vector ;
input_3 : in std_logic_vector ;
sel : in std_logic_vector (1 downto 0);
output : out std_logic_vector
);
end entity mux_4input;
They will inherit their width (and direction) from the signals they are conencted to in the instantiating entity.
It's probably not the right thing to do in this particular case of a mux, rick's answer is what I'd go for, but unconstrained arrays don't get mentioned much, so I thought I'd offer them! In this case, you'd probably also want some asserts to ensure that everything you've wired up is the same width.