VHDL synthesis of registers - separate process for each register vs. one merged process - vhdl

Question

Let's say I have two registers named reg_operand1 and reg_operand2. For both of them I have an appropriate write-enable signal. Somewhere I read I should have separate process for each register assignment, something like this:
process(CLK, RESET)
begin
if (RESET = '1') then
reg_operand1 <= (others => '0');
elsif (CLK'event and CLK = '1') then
if reg_operand1_we='1' then
reg_operand1 <= DI;
end if;
end if;
end process;
process(CLK, RESET)
begin
if (RESET = '1') then
reg_operand2 <= (others => '0');
elsif (CLK'event and CLK = '1') then
if reg_operand2_we='1' then
reg_operand2 <= DI;
end if;
end if;
end process;
But what happen if I merge the processes into this? Will the synthesized circuit be different? Also, what if I put "elsif" between the if-statements in merged process? Will the synthesizer insert a multiplexor into the circuit? Thanks!
process(CLK, RESET)
begin
if (RESET = '1') then
reg_operand1 <= (others => '0');
reg_operand2 <= (others => '0');
elsif (CLK'event and CLK = '1') then
if reg_operand1_we='1' then
reg_operand1 <= DI;
end if;
if reg_operand2_we='1' then
reg_operand2 <= DI;
end if;
end if;
end process;

Answer 1

The second one will produce exactly the same hardware as the first, and as already been said, contains less boilerplate.
If I understand your question about elsif correctly, you're proposing:
process(CLK, RESET)
begin
if (RESET = '1') then
reg_operand1 <= (others => '0');
reg_operand2 <= (others => '0');
elsif (CLK'event and CLK = '1') then
if reg_operand1_we='1' then
reg_operand1 <= DI;
elsif reg_operand2_we='1' then
reg_operand2 <= DI;
end if;
end if;
end process;
This generates different hardware, and also gives different behaviour.
In the example without the elsif, reg_operand2 is assigned DI when reg_operand2_we is high, irrespective of the state of reg_operand1_we.
When elsif is used, the assignment to of reg_operand2 only occurs when reg_operand2_we is high and reg_operand1_we is low
In general, if the two assignments do not depend on each other, use a seperate if construct.

Answer 2

The second one is shorter and simpler, and will generate the same hardware. (from a brief inspection : i.e. assuming there are no accidental typos in one or the other)
An elsif in the second version, combining the two register writes, will just prioritise the registers; i.e. if you attempt to write to both registers by asserting both we signals in the same cycle, only reg_operand1 will actually be written. It will have no other effect on the design.
So...
Unless you have specific corporate style guides that prohibit it, use the second style as a general rule.
There may be a FEW cases where you want to COMPLETELY separate some functionality to make it clear that it IS separate; in that case it's better not to be dogmatic about this style; but USUALLY fewer lines of code means less to go wrong, especially where (as here) it's easier to read and understand.
"I read somewhere" ... it would be worth knowing where you read this. There are a LOT of excruciatingly bad books, teaching materials and example projects out there, waiting to ruin potential VHDL programmers, and it's worth publicising which ones to avoid...