I want always call top-level makefile with same command line. I tried:
.PHONY: %
%:
$(MAKE) -C ${CURDIR}/.. ${CURDIR}/$*
but its does not work :(
I'm not sure what you're trying to do. Are you saying that for any invocation of make in this directory you want to run make in a different directory, with the same arguments?
You can't quite do this, but this will get you close:
.DEFAULT:
$(MAKE) -C ${CURDIR}/.. $#
I don't know why you were prefixing the $* with $(CURDIR) in the target name...?
The big difference between this and the original invocation is that it will run a separate make process for each target; that is if you run make foo bar it will invoke the "top-level makefile" twice: once with a target of foo and then again with a target of bar. There's no way to avoid this, that I can think of.
Related
I want to troubleshoot Makefile. A lot of commands are hidden using the # prefix. e.g.
all:
#echo "building..."
how can I tell make to show all the commands? I tried the -d option and it does not show hidden commands.
Maybe try running make with V=1 or VERBOSE=1
I'm not exactly sure this is what you are looking for, but here is a related technique:
Prefixing commands with # in a makefile recipe can be convenient, so output does not get too much cluttered, but, as you may have discovered, in some situations it can be useful to actually see what command is executed.
One solution is to avoid using the # character in a makefile but use instead a variable. Say, a one-letter one. Say L, for "log output" (but its your choice).
Then, prefix all your commands in your makefile with that variable:
target: prerequ
$(L)do_this $< $#
$(L)do_that $< $#
An simply define the variable, using some command-line switch:
ifeq "$(LOG)" ""
LOG=no
endif
ifeq "$(LOG)" "Y"
L=#
endif
Then, you can launch make from the shell like this $make target (no logging) or like this:
$ make target LOG=Y
And all the executed commands will show up!
I have such code snippet:
.PHONY: program1 program2
a=A
b=B
c=C
program1:
#python example.py a=$(a) b=$(b)
program2:
program1 c=$(c) d=d
Due to the DRY principle, I don't want to replicate code and composed program2 in a way calling program1.
But I understand that program1 is not in a path.
How can I correctly define program2 target?
The recipe of a rule contains shell commands. make does not execute them directly. The shell it uses to execute them does not recognize make target names as commands any more than any other shell does, so a recipe cannot use make targets as commands.
But a recipe can run make, a procedure conventionally described as "recursive make". For example, this rule would achieve what I think you are describing:
program2:
$(MAKE) program1 c='$(c)' d=d
The MAKE variable will normally expand to the name of make command you used -- often just make, but perhaps something like gmake or /special/path/make. You can also redefine it yourself inside the makefile, maybe to add flags to it, for example.
I know what make clean does.
But what does make $* clean do?
I'm not able to find a clear explanation anywhere.
As Ross says, we can't help because you haven't provided enough context. You need to provide at least the rule in which the make $* clean appears.
However, I'll guess it looks something like this:
%.xyz:
make $* clean
Here, $* is an automatic variable which will expand to the stem of the target (the text matching the % in the pattern). So, if you invoke make foobar.xyz, this rule would invoke make foobar clean: it would run a sub-make, build the foobar target, then build the clean target.
I've not seen anything quite like the above, although I can think of reasons for doing it. Far more common would be if you mistyped the command and it really said make -C $* clean, giving a rule like this:
%.xyz:
make -C $* clean
(note you should never use the static string make when invoking a sub-make; you should always use $(MAKE) or ${MAKE}). In this example running make foobar.xyz would run make -C foobar clean, which means change to the directory foobar and run the clean target there.
If it is invoked from a shell script, then $* is expanded to the arguments passed to the shell script.
#!/usr/bin/env bash
# filename clean.sh
make $* clean
The above shell script can be invoked like,
#./clean.sh --silent
Which will eventually pass the --silent to the make application and execute the following command.
#make --silent clean
Finally, $* in a shell-script is expanded by the shell, not by the make application.
If I run make clean twice the second invocation will build the dependency Makefiles that are scheduled for removal. How can I get Makefile to recognize the files scheduled for removal and skip the recursive call to make for that directory? In other words, only make clean in sub directory if the makefile already exists in each sub directory, on a per sub directory basis. I don't know the GNU-Make syntax but I'm looking for something like:
Dependencies=[dependency1,dependency2,dependency3,dependency4]
DoNotMake=[bool1,bool2,bool3,bool4]
for all (i < 4):
if (! Dependencies(i)/Makefile):
DoNotMake(i)=true
The current rules for make clean are as follows:
.PHONY: clean
clean:
$(MAKE) MAKEDEPEND=off SUBDIR_ARGS=clean
rm -f dependency1/Makefile
rm -f dependency2/Makefile
rm -f dependency3/Makefile
rm -f dependency4/Makefile
rm -f dependency4/src/config.h.in
I can't give you a definite answer since there's still a lot of your makefile that you haven't posted, but here are some things that we do to solve similar problems.
The make variable MAKECMDGOALS contains the current make target. If you want to avoid doing something when you run make clean, you can do something like this:
ifeq (,$(findstring $(MAKECMDGOALS),clean))
# Whatever you place here won't be run when you run 'make clean'
endif
You can also add a bit of shell script to only invoke a sub-makefile when it exists:
some_target:
[ -f $(SUB_FOLDER)/Makefile ] && $(MAKE) -C $(SUB_FOLDER)
If your makefiles are being created implicitly, then these may not work. You may be able to use the --assume-old= option to prevent make from re-building the makefiles (I've never tried to use that on a file that doesn't exist, so YMMV).
I want to tell make that it shall always use -j4 option even if I didn't specify it vie command line. Normally i would do this in some configuration file (i.e. ~/.makerc).
Does such file exist for gnu make?
Have a read about the $(MAKEFLAGS) variable:
export MAKEFLAGS=j4
However this will likely interfere with recursive-make-based builds (not that sensible people are using recursive make anyway!), by interfering with GNU make's ability to communicate with its sub-makes.
So the more sensible approach is probably a wrapper script or an alias or shell function.
Well, yes and no --- normally you would use an include file. Put your common configuration items together in a file, say common.mk and add
include common.mk
at the top of your makefile. If the flag doesn't have a matching way to configure it from inside the make file, you can use a function
function mk {
make -j4 $*
}
It doesn't exist, but you can do this by having a recursive call into make.
For example:
Makefile:
-include $(HOME)/.makerc
.DEFAULT_GOAL: all
# This will handle a default goal if make is just called without any target
all:
$(MAKE) $(MAKE_OPTIONS) -f Makefile.real $(MAKECMDGOALS)
# This handles all targets and passes it through
%:
$(MAKE) $(MAKE_OPTIONS) -f Makefile.real $(MAKECMDGOALS)
$(HOME)/.makerc:
MAKE_OPTIONS := -j4
I would like to expand a bit on the solution hinted in John Marshall's answer.
You can simply put a one-line wrapper script somewhere earlier in the $PATH with the following contents:
#!/bin/bash
$(type -ap make | sed -n 2p) -j4 "$#"
(The script doesn't have to be named make, and that would make it simpler, but I find it convenient if it is.)
I would argue that this is better than the other approaches for the following reasons:
Unlike MAKEFLAGS approach, it does not break recursive builds (which are actually quite common in my experience).
Unlike include .makerc approach, it can be applied locally without changing any existing makefiles or your workflow in any way.
Unlike shell alias or function approach, it is shell-agnostic (doesn't tie you to any particular shell) and works in any additional build scripts that you might have to use, too, as long as you launch them in the same environment.
I like the MAKEFLAGS approach suggested by John Marshall in lieu of make supporting something like an automatic .makerc project config file. However, I didn't want to have to remember to source a .env or similar environment variables beforehand (and unsetting them afterward).
A solution to this is to put the MAKEFLAGS assignment at the top of the Makefile itself:
#!/usr/bin/env make
MAKEFLAGS=s
.PHONY: foo
foo:
echo "hello, make"
Run it:
$ make foo
hello, make
Compared to running without the MAKEFLAGS=... line:
$ make foo
echo "hello, make"
hello, make