VHDL Adder Test Bench - vhdl

Question

I'm new to VHDL and I'm making a 4bit adder using 4 Full Adders. I created a test bench to see if the adder is working and in the ans I'm getting values of UUUU. From what I read is that the process is not being executed. I have no idea how to fix this, any help would be appreciated.
Here is the TestBench
ENTITY Adder4_Test IS
END Adder4_Test;
ARCHITECTURE behavior OF Adder4_Test IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT Adder4
PORT(
X : IN STD_LOGIC_vector(3 downto 0);
Y : IN STD_LOGIC_vector(3 downto 0);
Ans : OUT STD_LOGIC_VECTOR(3 downto 0);
Cout : OUT STD_LOGIC
);
END COMPONENT;
--Inputs
signal X : STD_LOGIC_vector(3 downto 0) := (others => '0');
signal Y : STD_LOGIC_vector(3 downto 0) := (others => '0');
--Outputs
signal Ans : STD_LOGIC_vector(3 downto 0);
signal Cout : STD_LOGIC;
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
--constant <clock>_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: Adder4 PORT MAP (
X,
Y,
Ans,
Cout
);
-- Clock process definitions
--<clock>_process :process
--begin
--<clock> <= '0';
--wait for <clock>_period/2;
--<clock> <= '1';
--wait for <clock>_period/2;
--end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
--wait for 100 ns;
--wait for <clock>_period*10;
-- insert stimulus here
-- Case 1 that we are testing.
X <= "0000";
Y <= "0000";
wait for 10 ns;
assert ( Ans = "0000" )report "Failed Case 1 - Ans" severity error;
assert ( Cout = '0' ) report "Failed Case 1 - Cout" severity error;
wait for 40 ns;
-- Case 2 that we are testing.
X <= "1111";
Y <= "1111";
wait for 10 ns;
assert ( Ans = "1110" )report "Failed Case 2 - Ans" severity error;
assert ( Cout = '1' ) report "Failed Case 2 - Cout" severity error;
wait for 40 ns;
wait;
end process;
END;
Here is the Adder4
entity Adder4 is
Port ( X : in STD_LOGIC_vector (3 DOWNTO 0);
Y : in STD_LOGIC_vector (3 DOWNTO 0);
Ans: out STD_LOGIC_vector (3 DOWNTO 0);
Cout: out STD_LOGIC);
end Adder4;
architecture Structure of Adder4 is
component FullAdder is
Port ( X : in STD_LOGIC;
Y : in STD_LOGIC;
Cin : in STD_LOGIC;
Sum : out STD_LOGIC;
Cout : out STD_LOGIC);
end component;
signal c0, c1, c2, c3: STD_LOGIC;
begin
c0 <='0';
b_adder0: FullAdder port map (X(0), Y(0), c0, Ans(0), c1);
b_adder1: FullAdder port map (X(1), Y(1), c1, Ans(1), c2);
b_adder2: FullAdder port map (X(2), Y(2), c2, Ans(2), c3);
b_adder3: FullAdder port map (X(3), Y(3), c3, Ans(3), Cout);
end Structure;
Here is the FullAdder
entity FullAdder is
Port ( X : in STD_LOGIC;
Y : in STD_LOGIC;
Cin : in STD_LOGIC;
Sum : out STD_LOGIC;
Cout : out STD_LOGIC);
end FullAdder;
architecture Behavioral of FullAdder is
component Xor_Model is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
C : in STD_LOGIC;
Z : out STD_LOGIC);
end component;
begin
Cout <= ((X and Y) or (Y and Cin) or (X and Cin));
Sum <= (X AND (NOT Y) AND (NOT Cin)) OR ((NOT X) AND Y AND (NOT Cin)) OR
((NOT X) AND (NOT Y) AND Cin) OR (X AND Y AND Cin) after 5ns;
xorLabel: Xor_Model
Port Map ( A => X, B => Y, C => Cin, Z => Sum);
end Behavioral;

Answer 1

After adding context clauses you didn't supply, separating 5ns into 5 ns and insuring the entities needed in Addr4 were analyzed in the right order, I tried to run a simulation using ghdl where I promptly got an error message"
Adder4.vhdl:28:1:warning: component instance "xorlabel" is not bound
Adder4.vhdl:12:15:warning: (in default configuration of fulladder(behavioral))
This for the FullAdder. Seeing it was a 3 input XOR, I added one:
library ieee;
use ieee.std_logic_1164.all;
entity Xor_model is
Port (A: in std_logic;
B: in std_logic;
C: in std_logic;
Z: out std_logic
);
end entity;
architecture behavioral of Xor_model is
begin
Z <= A xor B xor C;
end behavioral;
There were 'U's on ans until 5 ns, from the Sum assignment delay in FullAdder.
I got 'X's at 50 ns on ans cleared 5 ns later from the same delayed assignment. Notice the LSB is '0' due to a short circuit logical operator.
Adding FF to FF got FE (correct without regards to carryout which showed up correctly as '1').
Getting rid of the initial 'U's could be done one of two ways. Either assign a known value to Sum as a default value instead of relying on the default, or removing the delay in the assignment to Sum.
The 'X's are dependent on Sum from the FullAdders as well, there are transitions on inputs while waiting for 5 ns.
In a behavioral combinatoric model delays aren't particularly expressive, in particular when you don't use delays for sub terms. If you delay contributing signals all along then signal path for a particular net based on gate delays, Sum would show up at the correct cumulative delay time. You could also use an intermediary Sum (with a different signal name) generated without delay and assign it to the output port Sum after a delay, eliminating the 'X's. Move the after 5 ns from FullAdder to Adder4:
In FullAdder:
((NOT X) AND (NOT Y) AND Cin) OR (X AND Y AND Cin) ; --after 5 ns;
In Adder4:
architecture Structure of Adder4 is
signal sum: std_logic_vector(3 downto 0);
b_adder0: FullAdder port map (X(0), Y(0), c0, sum(0), c1);
b_adder1: FullAdder port map (X(1), Y(1), c1, sum(1), c2);
b_adder2: FullAdder port map (X(2), Y(2), c2, sum(2), c3);
b_adder3: FullAdder port map (X(3), Y(3), c3, sum(3), Cout);
And add delay assigning sum to the ans:
Ans <= sum after 5 ns;
And where if you set a default value of '0's on Ans in the Adder4 port:
Ans: out STD_LOGIC_vector (3 DOWNTO 0) := (others => '0');
You can get rid of the initial 'U's:
And to clarify the 'U's are there until there is a transaction on the output (Ans) following the after 5 ns delay. It might be more proper to use (others => 'X')