So I am trying to do a 4 bit adder and have ran into an error I can't seem to figure out.
Error (10430): VHDL Primary Unit Declaration error at adder1.vhd(3): primary unit "Adder1Vhd" already exists in library "work"
I have a project called 4 bit adder and inside that project folder is the .vhd file for Adder1.vhd. Here is the codes I have, if somebody could help me figure this out it would be greatly appreciated.
Adder4.vhd:
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY Adder4 IS
GENERIC(CONSTANT N: INTEGER := 4);
PORT(
a, b: IN STD_LOGIC_VECTOR(N-1 DOWNTO 0); -- Input SW[7..4]: a[3..0] inputs,
-- SW[3..0]: b[3..0]
cIn: in std_logic;
sum: OUT STD_LOGIC_VECTOR(N-1 DOWNTO 0); -- Output LEDR[3..0]
cOut: OUT STD_LOGIC -- Output LEDR[4]
);
END Adder4;
ARCHITECTURE imp OF Adder4 IS
COMPONENT Adder1
PORT(
a, b, cIn : in STD_LOGIC;
sum, cOut : out STD_LOGIC);
END COMPONENT;
SIGNAL carry_sig: std_logic_vector(N-1 DOWNTO 0);
BEGIN
A1: Adder1 port map (a(0), b(0), cIn, sum(0), carry_sig(0));
A2: Adder1 port map (a(1), b(1), carry_sig(0), sum(1), carry_sig(1));
A3: Adder1 port map (a(2), b(2), carry_sig(1), sum(2), carry_sig(2));
A4: Adder1 port map (a(3), b(3), carry_sig(2), sum(3), cOut);
END imp;
Adder1.vhd(the file inside the Adder4 project folder):
library ieee;
use ieee.std_logic_1164.all;
entity Adder1Vhd is
port(
a, b, cIn : in std_logic;
sum, cOut : out std_logic);
end Adder1Vhd;
architecture imp of Adder1Vhd is
begin
-- Add two lines (one for sum and the other for cOut) of VHDL code here
sum <= (a xor b) xor cIn;
cOut <= (a and b) or (cIn and (a xor b));
end imp;
There is another file that has an entity named Adder1Vhd in the library work (current work library). You can either delete the file on disk or just remove it from the library work in the file navigator of Quartus II.
By the way, it's a good convention to save a VHDL files using the same name as the entity.
And the name of a component must be the name of it's entity, not the filename. So,
COMPONENT Adder1 -- here 'Adder1' should be 'Adder1Vhd'
PORT(
a, b, cIn : in STD_LOGIC;
sum, cOut : out STD_LOGIC);
END COMPONENT;
Component instantiation statements are the same.
Related
please I need some help with my VHDL code. I am trying to design a Full adder circuit with 2 half adders. I’m using Max Plus II for my design. I have tried compiling but I keep getting errors(node instance instantiates undefined entity). Please I would appreciate any help I can get. Also, I'm very new to VHDL. Kind regards.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity full_adder is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
cin : in STD_LOGIC;
sum : out STD_LOGIC;
cout : out STD_LOGIC);
end full_adder;
architecture Behavioral of full_adder is
component half_adder is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
sum : out STD_LOGIC;
cout : out STD_LOGIC);
end component;
signal s1, s2 : STD_LOGIC;
signal c1, c2 : STD_LOGIC;
begin
HA1: half_adder port map (a => a, b => b, sum => s1, cout => c1);
HA2: half_adder port map (a => s1, b => cin, sum => s2, cout => c2);
sum <= s2;
cout <= c1 OR c2;
end Behavioral;
I expect to design a full adder using 2 half adders and an OR gate. I would also like to view the Wave simulation.
Though you have a component statement which defines the interface of your half_adder block, you will need an equivalent entity statement (usually found in its own file) to actually define its inner workings.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity half_adder is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
sum : out STD_LOGIC;
cout : out STD_LOGIC);
end half_adder;
architecture dataflow of half_adder is
begin
cout <= a and b;
sum <= a xor b;
end dataflow;
The component statement tells your compiler to look for a module that matches a specific description; the entity statement actually defines the workings of the module itself.
I've a VHDL code with a top entity and several other entities. Now there is an output in one of the subentities of which the value has to be brought to the toplevel entity to show it in my simulation program.
How can i do that?
TOP entity:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity multiplier is
port( Clk : in std_logic; -- Clock
A,B : in std_logic_vector(7 downto 0); -- A and B
Start : in std_logic; -- Start
Y : buffer std_logic_vector(15 downto 0); -- Result of A * B
Ready : out std_logic); -- Ready
end multiplier;
architecture structural of multiplier is
-- declaration of signals between different sub-circuits inside the multiplier
signal smInit, smCheck, smAdd, smShift, smZero, smReady, Stop : std_logic;
signal SR_A, SR_B, ADDout, MUXout : std_logic_vector(15 downto 0);
begin
io01: Ready <= smReady;
-- Instantiation of the FSM controller
sm01: entity work.FSM port map( Start, Stop, SR_A(0), Clk,
smReady, smInit, smCheck, smAdd, smShift, smZero);
-- Instantiation of the other sub-circuits and their connections
SR1: entity work.Shifter port map(smInit, smShift, '0', Clk, A, SR_A);
SR2: entity work.Shifter port map(smInit, smShift, '1', Clk, B, SR_B);
A1: entity work.Add16 port map(SR_B, Y, ADDout);
M1: entity work.Mux16 port map(smAdd, ADDout, Y, MUXout);
G1: entity work.Reg16 port map(smInit, Clk, MUXout, Y);
Z1: entity work.AllZero port map(SR_A(7 downto 0), Stop);
end structural; -- end of the multiplier architecture`
Now in the following subentity there is output S which i need to be able to call in the toplevel entity:
library IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity Add16 is
port( A, B : in std_logic_vector(15 downto 0);
S : buffer std_logic_vector(15 downto 0));
end Add16;
architecture behavior of Add16 is
signal Addout : out std_logic_vector (15 downto 0);
begin
S <= A + B;
end behavior;
How do i do that?
VHDL-2008 has a "external names" concept, whereby a hierarchical reference is possible, so you don't need to manually route internal signals through the hierarchy if the test bench needs access to the value.
If the top-level test bench name is tb and the multiplier instance name is multiplier_e then an alias for the S port on Add16 can be created in the test bench using:
alias S_tb is <<signal .tb.multiplier_e.A1.S : std_logic_vector(15 downto 0)>>;
I am trying to connect the output of an entity to the input of another entity.
Eventually connect a third entity will be connected,but i want to understand the process of connecting two entity's together.
Do I use a port map? If I do, are they added to both architectures of the different entity's to link them?
I know it wont be as simple as below:
link: transmitter port map (output_e1=>input_e2);
I have tried this but an error returns using ModelSim pointing at components declarations!
update:
ENTITY transmitter is
port(
transmission : out STD_LOGIC_VECTOR (31 downto 0)
);
end transmitter;
architecture Behavioral of transmitter is
end Behavioral;
Entity receiver is
PORT(
rxi:in signed (7 downto 0)
end receiver;
architecture Behavioral of receiver is
end Behavioral;
The above code does not include all the instructions and commands. My program works, but i have two entity and wish to link them as they would be in a communications system.
See the following example, a full adder circuit done using two half adders. You can see how the first half adder output is connected as the input of 2nd half adder.
--top module(full adder) entity declaration
entity fulladder is
port (a : in std_logic;
b : in std_logic;
cin : in std_logic;
sum : out std_logic;
carry : out std_logic
);
end fulladder;
--top module architecture declaration.
architecture behavior of fulladder is
--sub-module(half adder) is declared as a component before the keyword "begin".
component halfadder
port(
a : in std_logic;
b : in std_logic;
sum : out std_logic;
carry : out std_logic
);
end component;
--All the signals are declared here,which are not a part of the top module.
--These are temporary signals like 'wire' in Verilog.
signal s1,c1,c2 : std_logic:='0';
begin
--instantiate and do port map for the first half adder.
HA1 : halfadder port map (
a => a,
b => b,
sum => s1,
carry => c1
);
--instantiate and do port map for the second half adder.
HA2 : halfadder port map (
a => s1,
b => cin,
sum => sum,
carry => c2
);
carry <= c1 or c2; --final carry calculation
end;
See this link for explanation.
I tried to simulate a TFF using Xilinx ISE web pack and ModelSim using following block diagram and structural Code was written using VHDL. But I am unable to get the correct waveform. Due to the T-flip flop is sequential circuit, first I gave the output value as 1 or 0 for one output (Q) to start to the process.
T flip flop truth table and block diagram
simulation waveform
code for AND gate:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity AND_GATE is
Port ( X : in STD_LOGIC;
Y : in STD_LOGIC;
W : in STD_LOGIC;
Z : out STD_LOGIC);
end AND_GATE;
architecture Behavioral of AND_GATE is
begin
Z <= X AND Y AND W;
end Behavioral;
code for NOR gate:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity NOR_GATE is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
C : out STD_LOGIC);
end NOR_GATE;
architecture Behavioral of NOR_GATE is
begin
c <= A NOR B;
end Behavioral;
code for T-FF:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity TFF_2 is
Port ( T : in STD_LOGIC;
CLK : in STD_LOGIC;
Q : inout STD_LOGIC;
s : inout STD_LOGIC);
end TFF_2;
architecture STRUCTURAL of TFF_2 is
--declare components being used in T -FF
component TFF is
Port ( T : in STD_LOGIC;
CLK : in STD_LOGIC;
RST : in STD_LOGIC;
Q : out STD_LOGIC);
end component;
component NOR_GATE is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
C : out STD_LOGIC);
end component;
component AND_GATE is
Port ( X : in STD_LOGIC;
Y : in STD_LOGIC;
W : in STD_LOGIC;
Z : out STD_LOGIC);
end component;
--declare signals
signal S1, S2 : STD_LOGIC;
begin
C1 : AND_GATE port map (Q, T, CLK, S1);
C2 : AND_GATE port map (S, T, CLK, S2);
C3 : NOR_GATE port map (S1, S, Q);
C4 : NOR_GATE port map (S2, Q, S);
end STRUCTURAL;
These files synthesized without any errors but in the simulation expected output was not given.
There are a few suggestions I have.
There are non initialised variables. Add := '0'; at the end of the declarations. Simulation might show "X" or unknown. The Synthesised design will work OK, being the hardware will go to one or zero, but simulators need to be directed.
Some of your output variables have feedback into inputs. The design is asynchronous, being that you are not using a clock of some description to time the iterations. Consider using a process and something like if rising_edge(clk)
I'm learning VHDL and I've come to a halt. I'd like to create a simple gate out of smaller gates (a NAND gate here). Here's the code:
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity ANDGATE2 is
port(
x,y : in STD_LOGIC;
z : out STD_LOGIC
);
end ANDGATE2;
architecture ANDGATE2 of ANDGATE2 is
begin
z <= x AND y;
end ANDGATE2;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity NOTGATE1 is
port(
x : in STD_LOGIC;
z : out STD_LOGIC
);
end NOTGATE1;
architecture NOTGATE1 of NOTGATE1 is
begin
z <= NOT x;
end NOTGATE1;
library ieee;
use ieee.std_logic_1164.all;
entity NANDGATE2 is
port(
x : in STD_LOGIC;
y : in STD_LOGIC;
z : out STD_LOGIC
);
end NANDGATE2;
architecture NANDGATE2 of NANDGATE2 is
signal c, d: std_logic;
component NOTGATE1
port(
n_in : in STD_LOGIC;
n_out : out STD_LOGIC
);
end component;
component ANDGATE2
port(
a_in1, a_in2 : in STD_LOGIC;
a_out : out STD_LOGIC
);
end component;
begin
N0: ANDGATE2
port map(x, y, c);
N1: NOTGATE1
port map(c, d);
z <= d;
end NANDGATE2;
Here's the code from some tutorial I've been using as a template; it compiles with no problems.
library ieee;
use ieee.std_logic_1164.all;
-- definition of a full adder
entity FULLADDER is
port
(
a, b, c: in std_logic;
sum, carry: out std_logic
);
end FULLADDER;
architecture fulladder_behav of FULLADDER is
begin
sum <= (a xor b) xor c ;
carry <= (a and b) or (c and (a xor b));
end fulladder_behav;
-- 4-bit adder
library ieee;
use ieee.std_logic_1164.all;
entity FOURBITADD is
port
(
a, b: in std_logic_vector(3 downto 0);
Cin : in std_logic;
sum: out std_logic_vector (3 downto 0);
Cout, V: out std_logic
);
end FOURBITADD;
architecture fouradder_structure of FOURBITADD is
signal c: std_logic_vector (4 downto 0);
component FULLADDER
port
(
a, b, c: in std_logic;
sum, carry: out std_logic
);
end component;
begin
FA0: FULLADDER
port map (a(0), b(0), Cin, sum(0), c(1));
FA1: FULLADDER
port map (a(1), b(1), C(1), sum(1), c(2));
FA2: FULLADDER
port map (a(2), b(2), C(2), sum(2), c(3));
FA3: FULLADDER
port map (a(3), b(3), C(3), sum(3), c(4));
V <= c(3) xor c(4);
Cout <= c(4);
end fouradder_structure;
My code compiles with no errors, but with two warnings:
# Warning: ELAB1_0026: p2.vhd : (85, 0): There is no default binding for component "andgate2".(Port "a_in1" is not on the entity).
# Warning: ELAB1_0026: p2.vhd : (87, 0): There is no default binding for component "notgate1".(Port "n_in" is not on the entity).
What gives?
You need to use the same port names on your component and entity declarations.
Right now, for example in your NOTGATE1 entity declaration, you have input port x and output port z, but in the NANDGATE2 architecture, you declare the NOTGATE1 component to have ports n_in and n_out.
This won't cause problems during compilation, since compilation looks at a single unit at a time, and won't see the actual entities. In the elaboration phase, your tools will try to match up the entities to components, but this will fail since the ports don't match.
Not 100% sure, but I think the pins in your component declarations need to match up to the ones in your entity blocks:
component NOTGATE1
port(
x : in STD_LOGIC;
z : out STD_LOGIC
);
end component;
component ANDGATE2
port(
x,y : in STD_LOGIC;
z : out STD_LOGIC
);
Always use explicit port bindings in your port maps, like
port map(a_in1 => x,
a_in2 => y,
a_out => c);
It will make your code also more clear. In big projects it is the first rule of thumb.